Verification Design Engineer Salaries
71 verified profilesAverage salary is ₹27.3lakhs.
Employees as Verification Design Engineer earn an average of ₹27.3lakhs, mostly ranging from ₹14.2lakhs to ₹94.4lakhs based on 71 profiles.
| 👨💻 Male | ₹38lakhs Male Average Salary : ₹ 38 lakhs |
|---|---|
| 👩💻 Female | ₹14lakhs Female Average Salary : ₹ 14 lakhs |
Intel Corporation
Bengaluru | 3.8yrs | Base: ₹20.0lakhs Stocks: - Bonus: ₹2.8lakhs CTC:₹22.8lakhs | |||
Google
Bengaluru | 4yrs | ||||
Intel Corporation
Bengaluru | 6.9yrs | Base: ₹27.7lakhs Stocks: ₹6.3lakhs (Today) (141.3%) ₹15.2L Bonus: ₹1.3lakhs CTC:₹35.3lakhs (Today) (25.2%) ₹44.2L | |||
Google
Bengaluru | 8.2yrs | Base: ₹27.2lakhs Stocks: ₹9.7lakhs Bonus: - CTC:₹36.9lakhs | |||
Google
Bengaluru | ASIC Design Verification Engineer
(L4) Male | 7yrs | Base: ₹36.9lakhs Stocks: ₹40.7lakhs Bonus: ₹4.8lakhs CTC:₹82.4lakhs | ||
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Intel
Hyderabad | IP Design verification engineer
(7) Male | 7yrs | Base: ₹27.1lakhs Stocks: ₹5.8lakhs Bonus: ₹2.9lakhs CTC:₹35.8lakhs | ||
Intel
Bengaluru | SoC Design Verification Engineer
(Grade 6) Male | 7yrs | Base: ₹25.0lakhs Stocks: ₹5.1lakhs Bonus: ₹1.2lakhs CTC:₹31.3lakhs | ||
Intel
Bengaluru | SOC Design Verification Engineer
(Grade 8) Male | 17yrs | Base: ₹51.4lakhs Stocks: ₹14.7lakhs Bonus: ₹7.8lakhs CTC:₹74.0lakhs | ||
Analog Devices
Bengaluru | Associate Design Verification Engineer
(P1) Male | 0yrs | Base: ₹14.8lakhs Stocks: ₹0.5lakhs Bonus: - CTC:₹15.2lakhs | ||
Intel
Bengaluru | Analog and Design Verification Engineer
(Grade 6) Male | 5yrs | Base: ₹18.9lakhs Stocks: ₹4.1lakhs Bonus: ₹1.6lakhs CTC:₹24.6lakhs | ||
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How much do Verification Design Engineer employees make?
Employees as Verification Design Engineer earn an average of ₹27.3lakhs, mostly ranging from ₹14.2lakhs per year to ₹94.4lakhs per year based on 71 profiles. The top 10% of employees earn more than ₹60.8lakhs per year.
What is the average salary of Verification Design Engineer?
Average salary of an employee as Verification Design Engineer is ₹27.3lakhs.
What is the highest salary offered as Verification Design Engineer?
Highest reported salary offered as Verification Design Engineer is ₹102.9lakhs. The top 10% of employees earn more than ₹60.8lakhs per year. The top 1% earn more than a whopping ₹94.4lakhs per year.
What are the most common skills required as Verification Design Engineer?
13% of employees have skills in perl . 13% also know verilog . 10% also know c .
What are the highest paying jobs as Verification Design Engineer?
The top 5 highest paying jobs as Verification Design Engineer with reported salaries are:
senior design verification engineer - ₹46.0lakhs per year
hardware engineer - ₹45.0lakhs per year
ip design verification engineer - ₹39.0lakhs per year
soc design verification engineer - ₹21.0lakhs per year
design verification engineer - ₹21.0lakhs per year
What are the fresher salaries as Verification Design Engineer?
design verification engineer - ₹10.0lakhs per year
What is the median salary offered as Verification Design Engineer?
The median salary approximately calculated from salary profiles measured so far is ₹17.4lakhs per year.
How is the age distributed among employees as Verification Design Engineer?
11% of employees lie between 26-31 yrs . 7% of the employees fall in the age group of 21-26 yrs .
What qualifications do employees have as Verification Design Engineer?
10% hold a PostGraduate degree. 8% hold a Graduate degree.
Which schools do employees working as Verification Design Engineer went to?
4% of employees studied at Nalla Malla Reddy Engineering College . 3% studied at Birla Institute of Technology .
How much do Verification Design Engineer employees make?
Employees as Verification Design Engineer earn an average of ₹27.3lakhs, mostly ranging from ₹14.2lakhs per year to ₹94.4lakhs per year based on 71 profiles. The top 10% of employees earn more than ₹60.8lakhs per year.
What is the average salary of Verification Design Engineer?
Average salary of an employee as Verification Design Engineer is ₹27.3lakhs.
What is the highest salary offered as Verification Design Engineer?
Highest reported salary offered as Verification Design Engineer is ₹102.9lakhs. The top 10% of employees earn more than ₹60.8lakhs per year. The top 1% earn more than a whopping ₹94.4lakhs per year.
What are the most common skills required as Verification Design Engineer?
13% of employees have skills in perl . 13% also know verilog . 10% also know c .
What are the highest paying jobs as Verification Design Engineer?
The top 5 highest paying jobs as Verification Design Engineer with reported salaries are:
senior design verification engineer - ₹46.0lakhs per year
hardware engineer - ₹45.0lakhs per year
ip design verification engineer - ₹39.0lakhs per year
soc design verification engineer - ₹21.0lakhs per year
design verification engineer - ₹21.0lakhs per year
What are the fresher salaries as Verification Design Engineer?
design verification engineer - ₹10.0lakhs per year
What is the median salary offered as Verification Design Engineer?
The median salary approximately calculated from salary profiles measured so far is ₹17.4lakhs per year.
How is the age distributed among employees as Verification Design Engineer?
11% of employees lie between 26-31 yrs . 7% of the employees fall in the age group of 21-26 yrs .
What qualifications do employees have as Verification Design Engineer?
10% hold a PostGraduate degree. 8% hold a Graduate degree.
Which schools do employees working as Verification Design Engineer went to?
4% of employees studied at Nalla Malla Reddy Engineering College . 3% studied at Birla Institute of Technology .
| < 10 lakhs | < 10 lakhs Percentage : 15 |
|---|---|
| 10-20 lakhs | 10-20 lakhs Percentage : 42 |
| 20-30 lakhs | 20-30 lakhs Percentage : 10 |
| 30-40 lakhs | 30-40 lakhs Percentage : 13 |
| 40-50 lakhs | 40-50 lakhs Percentage : 6 |
| > 50 lakhs | > 50 lakhs Percentage : 14 |
| 21-26 yrs | 21-26 yrs Percentage : 7 |
|---|---|
| 26-31 yrs | 26-31 yrs Percentage : 11 |
| 31-36 yrs | 31-36 yrs Percentage : 7 |
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