Company	Title	Experience	Annual Salary	School	Skills
Microchip Technology Inc. Chennai	ASIC Verification Engineer	2.2yrs	Base: ₹11.8lakhs Stocks: - Bonus: - CTC:₹11.8lakhs	Model Engineering College Govt. Boys Higher Secondary School	Universal Verification Methodology (Uvm) Systemverilog Assertion Based Verification Functional Verification Code Coverage Verilog (Show More) Problem Solving Digital Electronics Formal Verification Linux Perl C C++ System On A Chip (Soc) Very-large-scale Integration (Vlsi) Application-specific Integrated Circuits (Asic) Microsoft Office Communication Engineering
AMD Hyderabad	Senior Silicon Design Engineer	6.6yrs		Veer Surendra Sai University Of Technology ( Formerly UCE ) Mother's Public School	Axi Microarchitecture Power Management Functional Verification Formal Verification Project Management (Show More) Systemverilog Universal Verification Methodology (Uvm) Application-specific Integrated Circuits (Asic) Research Digital Electronics Electronics Engineering Linux C C++ Management Microsoft Word Leadership Electronics And Telecommunications
Microchip Technology Inc. Chennai	Verification Engineer	2.2yrs	Base: ₹11.8lakhs Stocks: - Bonus: - CTC:₹11.8lakhs	Model Engineering College Govt. Boys Higher Secondary School	Universal Verification Methodology (Uvm) Systemverilog Verilog Assertion Based Verification Problem Solving Digital Electronics (Show More) Formal Verification Functional Verification Linux Perl C C++ System On A Chip (Soc) Very-large-scale Integration (Vlsi) Application-specific Integrated Circuits (Asic) Microsoft Office Communication Engineering
Qualcomm Bengaluru	Senior Staff Engineer	12.9yrs	Base: ₹71.1lakhs Stocks: ₹49.8lakhs (Today) (1.8%) ₹48.9L Bonus: ₹12.8lakhs CTC:₹133.7lakhs (Today) (0.7%) ₹132.8L	Indian Institute of Technology Savitribai Phule Pune University	Verilog Integrated Circuit Design Digital Signal Processors Matlab Vlsi C (Show More) Embedded C C++ Embedded Systems Microcontrollers Pcb Design Processors Circuit Design Fpga Uvm Formal Verification Assertion Based Verification Soc Very-large-scale Integration (Vlsi)
Intel Corporation Bengaluru	System - onChip Design Engineer Male	4.9yrs	Base: ₹22.2lakhs Stocks: ₹4.9lakhs (Today) (4.1%) ₹5.1L Bonus: ₹3.0lakhs CTC:₹30.1lakhs (Today) (0.7%) ₹30.3L	Institute of Technology Institute of Technology	Formal Verification Design Verification Test Planning Coverage Closer System Verilog Uvm (Show More) Perl Script
Texas Instruments Bengaluru	Digital Design Engineer (26)	3.8yrs	Base: ₹28.5lakhs Stocks: - Bonus: ₹4.4lakhs CTC:₹32.9lakhs	Government College of Technology Kongu Polytechnic College	Area Optimization Voltus Microarchitecture Tcsh Universal Verification Methodology (Uvm) Test Planning (Show More) Assertion Based Verification Field-programmable Gate Arrays (Fpga) Simvision Tempus Cadence Virtuoso Physical Design Innovus Genus Conformal Jasper Gold Python Xcelium Vim Bash Digital Circuit Design Rtl Design Conformal Lec Computer Hardware Troubleshooting Verilog Hdl Perl Git Linux Centos Windows Computer Hardware C Microsoft Word Microsoft Excel Microsoft Powerpoint Systemverilog Upf Tcl Modelsim Circuit Analysis Computer Hardware Assembly Computer Hardware Installation Rtl Coding Logic Synthesis Cdc Lint Static Timing Analysis Low-power Design Application-specific Integrated Circuits (Asic) Computer Architecture System On A Chip (Soc) Finite State Machines Rtl-to-gdsii Flow Formal Verification
Texas Instruments Bengaluru	Digital Design Engineer	3.7yrs	Base: ₹28.5lakhs Stocks: - Bonus: ₹4.4lakhs CTC:₹32.9lakhs	Government College of Technology Kongu Polytechnic College	Area Optimization Voltus Microarchitecture Tcsh Universal Verification Methodology (Uvm) Test Planning (Show More) Assertion Based Verification Field-programmable Gate Arrays (Fpga) Simvision Tempus Cadence Virtuoso Physical Design Innovus Genus Conformal Jasper Gold Python Xcelium Vim Bash Digital Circuit Design Rtl Design Conformal Lec Computer Hardware Troubleshooting Verilog Hdl Perl Git Linux Centos Windows Computer Hardware C Microsoft Word Microsoft Excel Microsoft Powerpoint Systemverilog Upf Tcl Modelsim Circuit Analysis Computer Hardware Assembly Computer Hardware Installation Rtl Coding Logic Synthesis Cdc Lint Static Timing Analysis Low-power Design Application-specific Integrated Circuits (Asic) Computer Architecture System On A Chip (Soc) Finite State Machines Rtl-to-gdsii Flow Formal Verification
Intel Santa Clara	Staff Engineer Male	16.3yrs		Indian Institute of Technology P.g. College of Law	Functional Verification Formal Verification Eda Systemverilog Perl Low Power Design (Show More) Tcl Soc Logic Synthesis Vlsi Asic Rtl Design Power Management Semiconductors Cadence Debugging Verilog Static Timing Analysis Cad Vhdl Physical Design Embedded Systems Open Verification Methodology Integrated Circuit Design Rtl Coding Amba Ahb Usb Analog Arm Timing Closure Modelsim Primetime Fpga Ncsim Ic Cmos Specman Dft
Cadence Design Systems Bengaluru	Design Engineer II Male	3.4yrs	Base: ₹17.6lakhs Stocks: - Bonus: ₹2.6lakhs CTC:₹20.2lakhs		Test Planning Scripting Hardware Design Problem Solving Microarchitecture Assertion Based Verification (Show More) Formal Verification Embedded C Jasper Sva Usb3.x Ltssm Systemverilog System On A Chip (Soc) Application-specific Integrated Circuits (Asic) Universal Verification Methodology (Uvm) Verilog C Matlab Simulink Xilinx Vivado Ni Labview Arduino Ide Jupyter C++ Python Vhdl Microsoft Office Management Leadership Teamwork English Urdu Hindi Code Composer Studio Systemverilog (Basics) Design Verification Soc Verifiction
Intel Corporation Hyderabad	IP Design Verification Engineer	7yrs	Base: ₹27.2lakhs Stocks: ₹5.8lakhs (Today) (10.3%) ₹6.4L Bonus: ₹2.9lakhs CTC:₹35.9lakhs (Today) (1.7%) ₹36.5L	Maven Silicon Softech Pvt. Ltd. Nalla Malla Reddy Engineering College	Universal Verification Methodology (Uvm) Verilog C Linux Perl System Verilog (Show More) Ovm Synopsys Vcs Verdi Open Verification Methodology Functional Verification Dve Assertions Assertion Based Verification Digital Electronics Jaspergold Formal Verification Microsoft Excel Microsoft Word Microsoft Office Management Customer Service

100% real time & verified!

Upgrade to view elite profiles

Okay, I'm in!Upgrade

Frequently asked questions

How much do Formal Verification employees make?

Employees who know Formal Verification earn an average of ₹35.3lakhs, mostly ranging from ₹20.8lakhs per year to ₹128.5lakhs per year based on 22 profiles. The top 10% of employees earn more than ₹48.1lakhs per year.

What is the average salary of Formal Verification?

Average salary of an employee who know Formal Verification is ₹35.3lakhs.

What is the highest salary offered who know Formal Verification?

Highest reported salary offered who know Formal Verification is ₹133.7lakhs. The top 10% of employees earn more than ₹48.1lakhs per year. The top 1% earn more than a whopping ₹128.5lakhs per year.

What are the most common skills required who know Formal Verification?

100% of employees have skills in formal verification . 0% also know verilog . 0% also know c .

What are the highest paying jobs who know Formal Verification?

The top 5 highest paying jobs who know Formal Verification with reported salaries are:

digital design engineer - ₹35.0lakhs per year
verification engineer - ₹15.0lakhs per year

Which are the top locations?

Bangalore

What is the median salary offered who know Formal Verification?

The median salary approximately calculated from salary profiles measured so far is ₹26.3lakhs per year.

How is the age distributed among employees who know Formal Verification?

27% of employees lie between 26-31 yrs . 27% of the employees fall in the age group of 31-36 yrs .

What qualifications do employees have who know Formal Verification?

41% hold a PostGraduate degree. 9% hold a Graduate degree.

Which schools do employees working who know Formal Verification went to?

14% of employees studied at Indian Institute of Technology . 14% studied at Indian Institute of Technology (IIT) .

Frequently asked questions

How much do Formal Verification employees make?

What is the average salary of Formal Verification?

Average salary of an employee who know Formal Verification is ₹35.3lakhs.

What is the highest salary offered who know Formal Verification?

What are the most common skills required who know Formal Verification?

100% of employees have skills in formal verification . 0% also know verilog . 0% also know c .

What are the highest paying jobs who know Formal Verification?

The top 5 highest paying jobs who know Formal Verification with reported salaries are:

digital design engineer - ₹35.0lakhs per year
verification engineer - ₹15.0lakhs per year

Which are the top locations?

Bangalore

What is the median salary offered who know Formal Verification?

The median salary approximately calculated from salary profiles measured so far is ₹26.3lakhs per year.

How is the age distributed among employees who know Formal Verification?

27% of employees lie between 26-31 yrs . 27% of the employees fall in the age group of 31-36 yrs .

What qualifications do employees have who know Formal Verification?

41% hold a PostGraduate degree. 9% hold a Graduate degree.

Which schools do employees working who know Formal Verification went to?

14% of employees studied at Indian Institute of Technology . 14% studied at Indian Institute of Technology (IIT) .

Salary Brackets

Percentage
10-20 lakhs	10-20 lakhs Percentage : 27
20-30 lakhs	20-30 lakhs Percentage : 27
30-40 lakhs	30-40 lakhs Percentage : 27
40-50 lakhs	40-50 lakhs Percentage : 9
> 50 lakhs	> 50 lakhs Percentage : 9

Age Brackets

Percentage
21-26 yrs	21-26 yrs Percentage : 23
26-31 yrs	26-31 yrs Percentage : 27
31-36 yrs	31-36 yrs Percentage : 27
36-41 yrs	36-41 yrs Percentage : 14
> 41 yrs	> 41 yrs Percentage : 5

Skills

Trending

formal verification

100 %

verilog

0 %

perl

0 %

assertion based verification

0 %

systemverilog

0 %

universal verification methodology (uvm)

0 %

Schools

Top

Indian Institute of Technology

14 %

Indian Institute of Technology (IIT)

14 %

Government College of Technology

9 %

Govt. Boys Higher Secondary School

9 %

Kongu Polytechnic College

9 %

Model Engineering College

9 %

Anna University

5 %

Formal Verification Salaries

Average salary is ₹35.3lakhs.

Similar Searches

How much do Formal Verification employees make?

What is the average salary of Formal Verification?

What is the highest salary offered who know Formal Verification?

What are the most common skills required who know Formal Verification?

What are the highest paying jobs who know Formal Verification?

Which are the top locations?

What is the median salary offered who know Formal Verification?

How is the age distributed among employees who know Formal Verification?

What qualifications do employees have who know Formal Verification?

Which schools do employees working who know Formal Verification went to?

How much do Formal Verification employees make?

What is the average salary of Formal Verification?

What is the highest salary offered who know Formal Verification?

What are the most common skills required who know Formal Verification?

What are the highest paying jobs who know Formal Verification?

Which are the top locations?

What is the median salary offered who know Formal Verification?

How is the age distributed among employees who know Formal Verification?

What qualifications do employees have who know Formal Verification?

Which schools do employees working who know Formal Verification went to?

Browse by Companies

Microsoft

Amazon

Google

Flipkart

Uber

Cisco Systems

NVIDIA

Oracle

Qualcomm

VMware

Browse by Titles

Software Engineer

Business Analyst

Product Manager

Engineering Manager

Data Scientist

UX Designer

Program Manager

Account Manager

Devops Engineer

Machine Learning Engineer

Browse by Skills

Java

JavaScript

Python

MySQL

Algorithms

AWS

Browse by Locations