Company	Title	Experience	Annual Salary	School	Skills
Microchip Technology Inc. Chennai	Verification Engineer	2.3yrs	Base: ₹11.8lakhs Stocks: - Bonus: - CTC:₹11.8lakhs	Model Engineering College Govt. Boys Higher Secondary School	Universal Verification Methodology (Uvm) Systemverilog Verilog Assertion Based Verification Problem Solving Digital Electronics (Show More) Formal Verification Functional Verification Linux Perl C C++ System On A Chip (Soc) Very-large-scale Integration (Vlsi) Application-specific Integrated Circuits (Asic) Microsoft Office Communication Engineering
Texas Instruments Bengaluru	Digital Design Engineer	4.1yrs	Base: ₹28.5lakhs Stocks: - Bonus: ₹4.4lakhs CTC:₹32.9lakhs	Government College of Technology Kongu Polytechnic College	Power Analysis Area Optimization Voltus Microarchitecture Tcsh Universal Verification Methodology (Uvm) (Show More) Test Planning Assertion Based Verification Field-programmable Gate Arrays (Fpga) Simvision Tempus Cadence Virtuoso Physical Design Innovus Genus Conformal Jasper Gold Python Xcelium Vim Bash Digital Circuit Design Rtl Design Conformal Lec Computer Hardware Troubleshooting Verilog Hdl Perl Git Linux Centos Windows Computer Hardware C Microsoft Word Microsoft Excel Microsoft Powerpoint Systemverilog Upf Tcl Modelsim Circuit Analysis Computer Hardware Assembly Computer Hardware Installation Rtl Coding Logic Synthesis Cdc Lint Static Timing Analysis Low-power Design Application-specific Integrated Circuits (Asic) Computer Architecture System On A Chip (Soc) Finite State Machines Rtl-to-gdsii Flow Formal Verification
Intel Corporation Bengaluru	System - onChip Design Engineer Male	4.9yrs	Base: ₹22.2lakhs Stocks: ₹4.9lakhs (Today) (14.3%) ₹5.6L Bonus: ₹3.0lakhs CTC:₹30.1lakhs (Today) (2.3%) ₹30.8L	Institute of Technology Institute of Technology	Formal Verification Design Verification Test Planning Coverage Closer System Verilog Uvm (Show More) Perl Script
Qualcomm Bengaluru	Senior Staff Engineer	12.5yrs	Base: ₹71.1lakhs Stocks: ₹49.8lakhs (Today) (10.8%) ₹44.4L Bonus: ₹12.8lakhs CTC:₹133.7lakhs (Today) (4.0%) ₹128.3L	Indian Institute of Technology Savitribai Phule Pune University	Verilog Integrated Circuit Design Digital Signal Processors Matlab Vlsi C (Show More) Embedded C C++ Embedded Systems Microcontrollers Pcb Design Processors Circuit Design Fpga Uvm Formal Verification Assertion Based Verification Soc Very-large-scale Integration (Vlsi)
Texas Instruments Bengaluru	Digital Design Engineer (26)	3.8yrs	Base: ₹28.5lakhs Stocks: - Bonus: ₹4.4lakhs CTC:₹32.9lakhs	Government College of Technology Kongu Polytechnic College	Area Optimization Voltus Microarchitecture Tcsh Universal Verification Methodology (Uvm) Test Planning (Show More) Assertion Based Verification Field-programmable Gate Arrays (Fpga) Simvision Tempus Cadence Virtuoso Physical Design Innovus Genus Conformal Jasper Gold Python Xcelium Vim Bash Digital Circuit Design Rtl Design Conformal Lec Computer Hardware Troubleshooting Verilog Hdl Perl Git Linux Centos Windows Computer Hardware C Microsoft Word Microsoft Excel Microsoft Powerpoint Systemverilog Upf Tcl Modelsim Circuit Analysis Computer Hardware Assembly Computer Hardware Installation Rtl Coding Logic Synthesis Cdc Lint Static Timing Analysis Low-power Design Application-specific Integrated Circuits (Asic) Computer Architecture System On A Chip (Soc) Finite State Machines Rtl-to-gdsii Flow Formal Verification
Texas Instruments Bengaluru	Digital Design Engineer	3.7yrs	Base: ₹28.5lakhs Stocks: - Bonus: ₹4.4lakhs CTC:₹32.9lakhs	Government College of Technology Kongu Polytechnic College	Area Optimization Voltus Microarchitecture Tcsh Universal Verification Methodology (Uvm) Test Planning (Show More) Assertion Based Verification Field-programmable Gate Arrays (Fpga) Simvision Tempus Cadence Virtuoso Physical Design Innovus Genus Conformal Jasper Gold Python Xcelium Vim Bash Digital Circuit Design Rtl Design Conformal Lec Computer Hardware Troubleshooting Verilog Hdl Perl Git Linux Centos Windows Computer Hardware C Microsoft Word Microsoft Excel Microsoft Powerpoint Systemverilog Upf Tcl Modelsim Circuit Analysis Computer Hardware Assembly Computer Hardware Installation Rtl Coding Logic Synthesis Cdc Lint Static Timing Analysis Low-power Design Application-specific Integrated Circuits (Asic) Computer Architecture System On A Chip (Soc) Finite State Machines Rtl-to-gdsii Flow Formal Verification
Intel Santa Clara	Staff Engineer Male	16.3yrs		Indian Institute of Technology P.g. College of Law	Functional Verification Formal Verification Eda Systemverilog Perl Low Power Design (Show More) Tcl Soc Logic Synthesis Vlsi Asic Rtl Design Power Management Semiconductors Cadence Debugging Verilog Static Timing Analysis Cad Vhdl Physical Design Embedded Systems Open Verification Methodology Integrated Circuit Design Rtl Coding Amba Ahb Usb Analog Arm Timing Closure Modelsim Primetime Fpga Ncsim Ic Cmos Specman Dft
INTEL	Digital Design Engineer Male	14.6yrs	Base: ₹29.9lakhs Stocks: ₹5.1lakhs Bonus: ₹3.9lakhs CTC:₹38.9lakhs	Indian Institute of Technology Bengal Engineering and Science University	Verilog VLSI Formal Verification
IBM System and Technology Bangalore	Staff RD Er Male	4.7yrs	CTC:₹17.4lakhs	Visvesvaraya National Institute of Technology (NIT) West Bengal University of Technology (WBUT)	VHDL UVM C Digital IC Design Perl C++ (Show More) Formal Verification Verilog
Qualcomm India Bangalore	Lead Engineer Sr. Male	8yrs	CTC:₹23.0lakhs	Manipal University Madras University	Digital Circuit Design Formal Verification Verilog

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Frequently asked questions

How much do Formal Verification employees make?

Employees who know Formal Verification earn an average of ₹36.4lakhs, mostly ranging from ₹22.3lakhs per year to ₹129.2lakhs per year based on 19 profiles. The top 10% of employees earn more than ₹45.8lakhs per year.

What is the average salary of Formal Verification?

Average salary of an employee who know Formal Verification is ₹36.4lakhs.

Which are the top locations?

Bangalore

What is the median salary offered who know Formal Verification?

The median salary approximately calculated from salary profiles measured so far is ₹27.5lakhs per year.

How is the age distributed among employees who know Formal Verification?

26% of employees lie between 21-26 yrs . 26% of the employees fall in the age group of 26-31 yrs .

Frequently asked questions

How much do Formal Verification employees make?

What is the average salary of Formal Verification?

Average salary of an employee who know Formal Verification is ₹36.4lakhs.

Which are the top locations?

Bangalore

What is the median salary offered who know Formal Verification?

The median salary approximately calculated from salary profiles measured so far is ₹27.5lakhs per year.

How is the age distributed among employees who know Formal Verification?

26% of employees lie between 21-26 yrs . 26% of the employees fall in the age group of 26-31 yrs .

Salary Brackets

Percentage
10-20 lakhs	10-20 lakhs Percentage : 26
20-30 lakhs	20-30 lakhs Percentage : 26
30-40 lakhs	30-40 lakhs Percentage : 32
40-50 lakhs	40-50 lakhs Percentage : 5
> 50 lakhs	> 50 lakhs Percentage : 11

Age Brackets

Percentage
21-26 yrs	21-26 yrs Percentage : 26
26-31 yrs	26-31 yrs Percentage : 26
31-36 yrs	31-36 yrs Percentage : 26
36-41 yrs	36-41 yrs Percentage : 16
> 41 yrs	> 41 yrs Percentage : 5

Skills

Trending

formal verification

100 %

verilog

0 %

perl

0 %

uvm

0 %

assertion based verification

0 %

rtl design

0 %

Schools

Top

Government College of Technology

16 %

Indian Institute of Technology

16 %

Indian Institute of Technology (IIT)

16 %

Kongu Polytechnic College

16 %

Anna University

5 %

Bengal Engineering and Science University

5 %

Birla Institute of Technology and Science (BITS)

5 %

Formal Verification Salaries

Average salary is ₹36.4lakhs.

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How much do Formal Verification employees make?

What is the average salary of Formal Verification?

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What is the median salary offered who know Formal Verification?

How is the age distributed among employees who know Formal Verification?

How much do Formal Verification employees make?

What is the average salary of Formal Verification?

Which are the top locations?

What is the median salary offered who know Formal Verification?

How is the age distributed among employees who know Formal Verification?

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