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Formal Verification Bangalore Salaries

13 verified profiles

Last updated on April 9, 2025

Average salary is ₹33.0lakhs.

Employees who know Formal Verification in Bangalore earn an average of ₹33.0lakhs, mostly ranging from ₹20.6lakhs to ₹122.2lakhs based on 13 profiles.

👨‍💻 Male	₹24lakhs Male Average Salary : ₹ 24 lakhs
👩‍💻 Female	₹20lakhs Female Average Salary : ₹ 20 lakhs

For every ₹100 paid to men, women are paid ₹83

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Salary Profiles

Company	Title	Experience	Annual Salary	School	Skills
Qualcomm Bengaluru	Senior Staff Engineer	12.9yrs	Base: ₹71.1lakhs Stocks: ₹49.8lakhs (Today) (8.6%) ₹45.5L Bonus: ₹12.8lakhs CTC:₹133.7lakhs (Today) (3.2%) ₹129.4L	Indian Institute of Technology Savitribai Phule Pune University	Verilog Integrated Circuit Design Digital Signal Processors Matlab Vlsi C (Show More) Embedded C C++ Embedded Systems Microcontrollers Pcb Design Processors Circuit Design Fpga Uvm Formal Verification Assertion Based Verification Soc Very-large-scale Integration (Vlsi)
Intel Corporation Bengaluru	System - onChip Design Engineer Male	4.9yrs	Base: ₹22.2lakhs Stocks: ₹4.9lakhs (Today) (2.0%) ₹5.0L Bonus: ₹3.0lakhs CTC:₹30.1lakhs (Today) (0.3%) ₹30.2L	Institute of Technology Institute of Technology	Formal Verification Design Verification Test Planning Coverage Closer System Verilog Uvm (Show More) Perl Script
Texas Instruments Bengaluru	Digital Design Engineer (26)	3.8yrs	Base: ₹28.5lakhs Stocks: - Bonus: ₹4.4lakhs CTC:₹32.9lakhs	Government College of Technology Kongu Polytechnic College	Area Optimization Voltus Microarchitecture Tcsh Universal Verification Methodology (Uvm) Test Planning (Show More) Assertion Based Verification Field-programmable Gate Arrays (Fpga) Simvision Tempus Cadence Virtuoso Physical Design Innovus Genus Conformal Jasper Gold Python Xcelium Vim Bash Digital Circuit Design Rtl Design Conformal Lec Computer Hardware Troubleshooting Verilog Hdl Perl Git Linux Centos Windows Computer Hardware C Microsoft Word Microsoft Excel Microsoft Powerpoint Systemverilog Upf Tcl Modelsim Circuit Analysis Computer Hardware Assembly Computer Hardware Installation Rtl Coding Logic Synthesis Cdc Lint Static Timing Analysis Low-power Design Application-specific Integrated Circuits (Asic) Computer Architecture System On A Chip (Soc) Finite State Machines Rtl-to-gdsii Flow Formal Verification
Texas Instruments Bengaluru	Digital Design Engineer	3.7yrs	Base: ₹28.5lakhs Stocks: - Bonus: ₹4.4lakhs CTC:₹32.9lakhs	Government College of Technology Kongu Polytechnic College	Area Optimization Voltus Microarchitecture Tcsh Universal Verification Methodology (Uvm) Test Planning (Show More) Assertion Based Verification Field-programmable Gate Arrays (Fpga) Simvision Tempus Cadence Virtuoso Physical Design Innovus Genus Conformal Jasper Gold Python Xcelium Vim Bash Digital Circuit Design Rtl Design Conformal Lec Computer Hardware Troubleshooting Verilog Hdl Perl Git Linux Centos Windows Computer Hardware C Microsoft Word Microsoft Excel Microsoft Powerpoint Systemverilog Upf Tcl Modelsim Circuit Analysis Computer Hardware Assembly Computer Hardware Installation Rtl Coding Logic Synthesis Cdc Lint Static Timing Analysis Low-power Design Application-specific Integrated Circuits (Asic) Computer Architecture System On A Chip (Soc) Finite State Machines Rtl-to-gdsii Flow Formal Verification
Cadence Design Systems Bengaluru	Design Engineer II Male	3.4yrs	Base: ₹17.6lakhs Stocks: - Bonus: ₹2.6lakhs CTC:₹20.2lakhs		Test Planning Scripting Hardware Design Problem Solving Microarchitecture Assertion Based Verification (Show More) Formal Verification Embedded C Jasper Sva Usb3.x Ltssm Systemverilog System On A Chip (Soc) Application-specific Integrated Circuits (Asic) Universal Verification Methodology (Uvm) Verilog C Matlab Simulink Xilinx Vivado Ni Labview Arduino Ide Jupyter C++ Python Vhdl Microsoft Office Management Leadership Teamwork English Urdu Hindi Code Composer Studio Systemverilog (Basics) Design Verification Soc Verifiction
Intel Bangalore	Graphics Hardware Engineer Male	9yrs	CTC:₹18.0lakhs	Pune University	RTL Design Testing PNR FPGA prototyping Formal Verification
Qualcomm India Bangalore	Lead Engineer Sr. Male	8yrs	CTC:₹23.0lakhs	Manipal University Madras University	Digital Circuit Design Formal Verification Verilog
Intel Bangalore	Formal Verification Engineer Male	4.7yrs	CTC:₹22.0lakhs	Devi Ahilya Vishwa Vidhyalaya (DAVV) Indian Institute of Technology (IIT)	VHDL UVM ASIC Formal Verification Verilog
Interra Systems Bangalore	Senior Design Engineer Female	6yrs	CTC:₹16.2lakhs	Thapar Institute of Engineering and Technology (TIET) Rajasthan University	Gate Level Simulation Functional Verification Formal Verification
Samsung Research Institute Bangalore	Technical Leader Female	3.9yrs	CTC:₹20.0lakhs	Anna University Hyderabad University	Vulnerability Assessment C Information Security Mobile Payments Research Cryptography (Show More) Formal Verification

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Frequently asked questions

How much do Formal Verification Bangalore employees make?

Employees who know Formal Verification in Bangalore earn an average of ₹33.0lakhs, mostly ranging from ₹20.6lakhs per year to ₹122.2lakhs per year based on 13 profiles. The top 10% of employees earn more than ₹36.0lakhs per year.

What is the average salary of Formal Verification Bangalore?

Average salary of an employee who know Formal Verification in Bangalore is ₹33.0lakhs.

What is the median salary offered who know Formal Verification in Bangalore?

The median salary approximately calculated from salary profiles measured so far is ₹23.0lakhs per year.

How is the age distributed among employees who know Formal Verification in Bangalore?

38% of employees lie between 26-31 yrs . 38% of the employees fall in the age group of 31-36 yrs .

Frequently asked questions

How much do Formal Verification Bangalore employees make?

What is the average salary of Formal Verification Bangalore?

Average salary of an employee who know Formal Verification in Bangalore is ₹33.0lakhs.

What is the median salary offered who know Formal Verification in Bangalore?

The median salary approximately calculated from salary profiles measured so far is ₹23.0lakhs per year.

How is the age distributed among employees who know Formal Verification in Bangalore?

38% of employees lie between 26-31 yrs . 38% of the employees fall in the age group of 31-36 yrs .

Salary Brackets

Percentage
10-20 lakhs	10-20 lakhs Percentage : 23
20-30 lakhs	20-30 lakhs Percentage : 38
30-40 lakhs	30-40 lakhs Percentage : 31
> 50 lakhs	> 50 lakhs Percentage : 8

Age Brackets

Percentage
21-26 yrs	21-26 yrs Percentage : 15
26-31 yrs	26-31 yrs Percentage : 38
31-36 yrs	31-36 yrs Percentage : 38

Skills

Trending

formal verification

100 %

0 %

uvm

0 %

verilog

0 %

assertion based verification

0 %

perl

0 %

test planning

0 %

Schools

Top

Government College of Technology

15 %

Kongu Polytechnic College

15 %

Anna University

8 %

Devi Ahilya Vishwa Vidhyalaya (DAVV)

8 %

Gujarat University

8 %

Hyderabad University

8 %

Indian Institute of Technology

8 %

Formal Verification Bangalore Salaries

Average salary is ₹33.0lakhs.

Similar Searches

How much do Formal Verification Bangalore employees make?

What is the average salary of Formal Verification Bangalore?

What is the median salary offered who know Formal Verification in Bangalore?

How is the age distributed among employees who know Formal Verification in Bangalore?

How much do Formal Verification Bangalore employees make?

What is the average salary of Formal Verification Bangalore?

What is the median salary offered who know Formal Verification in Bangalore?

How is the age distributed among employees who know Formal Verification in Bangalore?

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