Company	Title	Experience	Annual Salary	School	Skills
Centre for Development of Telematics (C-DOT) Bengaluru	Digital Design Engineer (Scientist B)	1.9yrs	Base: ₹10.1lakhs Stocks: - Bonus: - CTC:₹10.1lakhs	Indian Institute of Technology Hyderabad (IIT-H) Institute of Engineering & Technology DAVV	System On A Chip (Soc) Modelsim Lattice Diamond Software Cadence Schematic Capture Analog Layout Keysight Ads (Show More) Oops Hyperlynx Power Hyperlynx Signal Integrity Cadence Pcb Designer C++ C Assertions Based Verification Systemverilog Cadence Allegro Verilog Cadence Virtuoso Xilinx Vivado Comsol Ltspice Asitic Clewin Constraints Rtl Design CDC Synchonizers Static Timing Analysis I2C SPI Uart FIFO CORDIC
eInfochips (An Arrow Company) Ahmedabad	ASIC Design Intern	0.2yrs	Base: ₹11.6lakhs Stocks: - Bonus: - CTC:₹11.6lakhs	NIRMA UNIVERSITY Bhulka vihar school	Altera Modelsim Timing Scripting Static Timing Analysis Rtl Coding (Show More) Hardware Architecture Problem Solving Electronic Engineering Microcontrollers Printed Circuit Board (Pcb) Design Electronic Components Hardware Testing Circuit Design Digital Logic Vhdl Analog Circuit Design Digital Electronics Field-programmable Gate Arrays (Fpga) Digital Designs C++ Computer Architecture Verilog Rtl Design Shell Scripting Very-large-scale Integration (Vlsi) Linux Codeforces
Signaltron India	Digital Design Engineer Male	1.7yrs	Base: ₹13.7lakhs Stocks: - Bonus: - CTC:₹13.7lakhs	Indian Institute of Technology Walchand College of Engineering(A Govt. Aided Autonomous Institute)	Pcie Gigabit Ethernet Cpri Systems Design I2c Hardware Design (Show More) Digital Hardware Design Communication Logic Design Digital Logic Digital Ic Design Digital Circuit Design Algorithm Design Verilog Rtl Design Axi Fpga Prototyping Static Timing Analysis Tcl Digital Designs Design Engineering Vhdl Cdc Very-large-scale Integration (Vlsi) Xilinx Embedded C Rtl Coding Digital Image Processing Python Silicon Functional Verification Field-programmable Gate Arrays (Fpga) Electrical Engineering Rtl Development Physical Design Interpersonal Skills Problem Solving Debugging Application-specific Integrated Circuits (Asic) Programming C C++ Matlab Html Microsoft Office Microsoft Powerpoint Microsoft Excel Microsoft Word Leadership Management Cadence Virtuoso Systemverilog
STMicroelectronics Noida	DRC Developer - subco (1)	1.1yrs	Base: ₹12.8lakhs Stocks: - Bonus: ₹4.6lakhs CTC:₹17.4lakhs	J.C. Bose University of Science and Technology R.D.M Saraswati public school	Semiconductor Fabrication Skill Coding Layout Design Cadence Virtuoso Application-specific Integrated Circuits (Asic) Problem Solving (Show More) Static Timing Analysis Team Management Patent Law Matlab Tkinter Arduino Ide Electronics Raspberry Pi Teamwork Microsoft Excel Team Leadership Management Printed Circuit Board (Pcb) Design Python Verilog Engineering Project Management English Research Marketing Training Communication Strategy Analytical Skills Creative Problem Solving Time Management Strategic Influence Field-programmable Gate Arrays (Fpga)
Texas Instruments Bengaluru	Analog Design Engineer (24)	1.7yrs	Base: ₹20.4lakhs Stocks: ₹2.0lakhs (Today) (10.0%) ₹1.8L Bonus: ₹4.1lakhs CTC:₹26.5lakhs (Today) (0.8%) ₹26.3L	Indian Institute of Technology Kharagpur	Design Engineering Mixed-signal Ic Design Integrated Circuits (Ic) Power Management Hardware Design Layout Design (Show More) Schematic Layout Versus Schematic (Lvs) Electronic Engineering Design Rule Checking (Drc) Problem Solving Electrical Engineering Communication Circuits Analog Circuit Design Analog Cadence Virtuoso Verilog Analog Signal Processing Analog Integrated Circuit Design Mixed-signal Integrated Circuits Digital Ic Design Static Timing Analysis Python
Ampere Pune	Physical Design Engineer	6.6yrs	Base: ₹27.5lakhs Stocks: ₹7.6lakhs Bonus: ₹3.8lakhs CTC:₹38.9lakhs	G.H. Raisoni College of Engineering(GHRCE) Nagpur University	Layout Versus Schematic (Lvs) Design Rule Checking (Drc) Physical Design Asic Vlsi Scripting (Show More) Debugging System On A Chip (Soc) Linux Perl Verilog Mentoring Static Timing Analysis Tcl Timing Closure Place & Route Floorplanning Clock Tree Synthesis Physical Verification Time Management
Intel Corporation Bengaluru	SoC Architect Male	8yrs		The University of Texas at Austin Delhi Technological University (Formerly DCE)	X86 System On A Chip (Soc) Interconnect Manageability System Architecture Ucie (Show More) Pcie Hardware Design Cache Coherency Operating Systems Python Machine Learning Axi Amba Ahb Apb Logic Synthesis Physical Design Dft Rtl Design Cdc Verilog Systemverilog Rdc Lint Arm Cortex-m Arm Architecture Functional Safety Iso 26262 Advanced Driver-assistance Systems (Adas) Requirements Traceability Microarchitecture Vlsi Cmos Vhdl Static Timing Analysis Embedded Systems C Robotics Matlab Image Processing Html 5 Css3 Javascript Html C++
Texas Instruments Bengaluru	Digital Design Engineer (26)	3.8yrs	Base: ₹28.5lakhs Stocks: - Bonus: ₹4.4lakhs CTC:₹32.9lakhs	Government College of Technology Kongu Polytechnic College	Area Optimization Voltus Microarchitecture Tcsh Universal Verification Methodology (Uvm) Test Planning (Show More) Assertion Based Verification Field-programmable Gate Arrays (Fpga) Simvision Tempus Cadence Virtuoso Physical Design Innovus Genus Conformal Jasper Gold Python Xcelium Vim Bash Digital Circuit Design Rtl Design Conformal Lec Computer Hardware Troubleshooting Verilog Hdl Perl Git Linux Centos Windows Computer Hardware C Microsoft Word Microsoft Excel Microsoft Powerpoint Systemverilog Upf Tcl Modelsim Circuit Analysis Computer Hardware Assembly Computer Hardware Installation Rtl Coding Logic Synthesis Cdc Lint Static Timing Analysis Low-power Design Application-specific Integrated Circuits (Asic) Computer Architecture System On A Chip (Soc) Finite State Machines Rtl-to-gdsii Flow Formal Verification
Texas Instruments Bengaluru	Digital Design Engineer	3.7yrs	Base: ₹28.5lakhs Stocks: - Bonus: ₹4.4lakhs CTC:₹32.9lakhs	Government College of Technology Kongu Polytechnic College	Area Optimization Voltus Microarchitecture Tcsh Universal Verification Methodology (Uvm) Test Planning (Show More) Assertion Based Verification Field-programmable Gate Arrays (Fpga) Simvision Tempus Cadence Virtuoso Physical Design Innovus Genus Conformal Jasper Gold Python Xcelium Vim Bash Digital Circuit Design Rtl Design Conformal Lec Computer Hardware Troubleshooting Verilog Hdl Perl Git Linux Centos Windows Computer Hardware C Microsoft Word Microsoft Excel Microsoft Powerpoint Systemverilog Upf Tcl Modelsim Circuit Analysis Computer Hardware Assembly Computer Hardware Installation Rtl Coding Logic Synthesis Cdc Lint Static Timing Analysis Low-power Design Application-specific Integrated Circuits (Asic) Computer Architecture System On A Chip (Soc) Finite State Machines Rtl-to-gdsii Flow Formal Verification
Synopsys Inc Bhubaneswar	Technical Engineer - Physical Design	1.9yrs	Base: ₹7.7lakhs Stocks: ₹1.9lakhs (Today) (15.8%) ₹1.6L Bonus: ₹1.0lakhs CTC:₹10.6lakhs (Today) (2.8%) ₹10.3L	Jaypee University of Engineering and Technology Mahatma Hansraj Modern School (MHMS)	Arduino Matlab Field-programmable Gate Arrays (Fpga) Fpga Layout Versus Schematic (Lvs) Analog Circuit Design (Show More) Computer Numerical Control (Cnc) Cmos Tcl Machine Learning Business Management Augmented Reality (Ar) Kotlin Mobile Applications Mobile Application Development Node.js Web Applications Heroku Web Development Django Python Digital Marketing Cloud Applications Cloud Vlsi Innovus Cadence Software Application-specific Integrated Circuits (Asic) Synopsys Primetime Amazon Ec2 Amazon S3 Cloud Storage Cloud Computing Iaas Image Processing Digital Image Processing Cloud Computing Amazon Web Services (Aws) Physical Design Synopsys Ic Compiler Static Timing Analysis Linux Perl Ltspice Glade C Cadence Virtuoso Very-large-scale Integration (Vlsi) Vhdl Arduino Ide Digital Electronics Integrated Circuits (Ic) Public Speaking C++ Team Leadership Microsoft Office Presentation Skills Unity Leadership

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Frequently asked questions

How much do Static Timing Analysis employees make?

Employees who know Static Timing Analysis earn an average of ₹32.9lakhs, mostly ranging from ₹16.0lakhs per year to ₹135.5lakhs per year based on 38 profiles. The top 10% of employees earn more than ₹62.4lakhs per year.

What is the average salary of Static Timing Analysis?

Average salary of an employee who know Static Timing Analysis is ₹32.9lakhs.

What is the highest salary offered who know Static Timing Analysis?

Highest reported salary offered who know Static Timing Analysis is ₹135.5lakhs. The top 10% of employees earn more than ₹62.4lakhs per year. The top 1% earn more than a whopping ₹135.5lakhs per year.

What are the most common skills required who know Static Timing Analysis?

100% of employees have skills in static timing analysis . 0% also know verilog . 0% also know c .

What are the highest paying jobs who know Static Timing Analysis?

The top 5 highest paying jobs who know Static Timing Analysis with reported salaries are:

lead member of technical staff - ₹136.0lakhs per year
staff engineer - ₹86.0lakhs per year
digital design engineer - ₹25.0lakhs per year
physical design engineer - ₹22.0lakhs per year
senior engineer - ₹20.0lakhs per year

Which are the top locations?

Bangalore

What is the median salary offered who know Static Timing Analysis?

The median salary approximately calculated from salary profiles measured so far is ₹19.6lakhs per year.

How is the age distributed among employees who know Static Timing Analysis?

37% of employees lie between 26-31 yrs . 32% of the employees fall in the age group of 31-36 yrs .

What qualifications do employees have who know Static Timing Analysis?

21% hold a PostGraduate degree. 11% hold a Graduate degree.

Which schools do employees working who know Static Timing Analysis went to?

11% of employees studied at Indian Institute of Technology . 8% studied at Indian Institute of Technology (IIT) .

Frequently asked questions

How much do Static Timing Analysis employees make?

What is the average salary of Static Timing Analysis?

Average salary of an employee who know Static Timing Analysis is ₹32.9lakhs.

What is the highest salary offered who know Static Timing Analysis?

What are the most common skills required who know Static Timing Analysis?

100% of employees have skills in static timing analysis . 0% also know verilog . 0% also know c .

What are the highest paying jobs who know Static Timing Analysis?

The top 5 highest paying jobs who know Static Timing Analysis with reported salaries are:

lead member of technical staff - ₹136.0lakhs per year
staff engineer - ₹86.0lakhs per year
digital design engineer - ₹25.0lakhs per year
physical design engineer - ₹22.0lakhs per year
senior engineer - ₹20.0lakhs per year

Which are the top locations?

Bangalore

What is the median salary offered who know Static Timing Analysis?

The median salary approximately calculated from salary profiles measured so far is ₹19.6lakhs per year.

How is the age distributed among employees who know Static Timing Analysis?

37% of employees lie between 26-31 yrs . 32% of the employees fall in the age group of 31-36 yrs .

What qualifications do employees have who know Static Timing Analysis?

21% hold a PostGraduate degree. 11% hold a Graduate degree.

Which schools do employees working who know Static Timing Analysis went to?

11% of employees studied at Indian Institute of Technology . 8% studied at Indian Institute of Technology (IIT) .

Salary Brackets

Percentage
10-20 lakhs	10-20 lakhs Percentage : 50
20-30 lakhs	20-30 lakhs Percentage : 18
30-40 lakhs	30-40 lakhs Percentage : 11
40-50 lakhs	40-50 lakhs Percentage : 3
> 50 lakhs	> 50 lakhs Percentage : 18

Age Brackets

Percentage
21-26 yrs	21-26 yrs Percentage : 21
26-31 yrs	26-31 yrs Percentage : 37
31-36 yrs	31-36 yrs Percentage : 32
36-41 yrs	36-41 yrs Percentage : 8
> 41 yrs	> 41 yrs Percentage : 3

Skills

Trending

static timing analysis

100 %

verilog

0 %

c++

0 %

perl

0 %

cadence virtuoso

0 %

vhdl

0 %

Schools

Top

Indian Institute of Technology

11 %

Indian Institute of Technology (IIT)

8 %

Birla Institute of Technology and Science

5 %

Birla Institute of Technology and Science (BITS)

5 %

Government College of Technology

5 %

Indian Institute of Technology (Indian School of Mines)

5 %

Jawaharlal Nehru Technological University (JNTU)

5 %

Static Timing Analysis Salaries

Average salary is ₹32.9lakhs.

Similar Searches

How much do Static Timing Analysis employees make?

What is the average salary of Static Timing Analysis?

What is the highest salary offered who know Static Timing Analysis?

What are the most common skills required who know Static Timing Analysis?

What are the highest paying jobs who know Static Timing Analysis?

Which are the top locations?

What is the median salary offered who know Static Timing Analysis?

How is the age distributed among employees who know Static Timing Analysis?

What qualifications do employees have who know Static Timing Analysis?

Which schools do employees working who know Static Timing Analysis went to?

How much do Static Timing Analysis employees make?

What is the average salary of Static Timing Analysis?

What is the highest salary offered who know Static Timing Analysis?

What are the most common skills required who know Static Timing Analysis?

What are the highest paying jobs who know Static Timing Analysis?

Which are the top locations?

What is the median salary offered who know Static Timing Analysis?

How is the age distributed among employees who know Static Timing Analysis?

What qualifications do employees have who know Static Timing Analysis?

Which schools do employees working who know Static Timing Analysis went to?

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