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Static Timing Analysis Bengaluru Salaries

31 verified profiles

Last updated on September 3, 2025

Average salary is ₹34.8lakhs.

Employees who know Static Timing Analysis in Bengaluru earn an average of ₹34.8lakhs, mostly ranging from ₹16.8lakhs to ₹139.1lakhs based on 31 profiles.

👨‍💻 Male	₹25lakhs Male Average Salary : ₹ 25 lakhs
👩‍💻 Female	₹21lakhs Female Average Salary : ₹ 21 lakhs

For every ₹100 paid to men, women are paid ₹84

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Salary Profiles

Company	Title	Experience	Annual Salary	School	Skills
NXP Semiconductors Bengaluru	Principal Design Engineer	10.2yrs		Ramaiah Institute Of Technology B. V. Bhoomaraddi College of Engg. & Tech.	Cdc Very-large-scale Integration (Vlsi) Rtl Coding System On A Chip (Soc) C Semiconductors (Show More) Verilog Vhdl Synthesis Static Timing Analysis Field-programmable Gate Arrays (Fpga) Microarchitecture Pcie Axi Application-specific Integrated Circuits (Asic) Asic Lint Rtl Design
Cisco Bengaluru	ASIC Engineer	6.1yrs	Base: ₹26.1lakhs Stocks: ₹9.6lakhs (Today) (6.2%) ₹10.2L Bonus: ₹2.0lakhs CTC:₹37.7lakhs (Today) (1.6%) ₹38.3L	National Institute of Technology Durgapur	Digital Designs Verilog Application-specific Integrated Circuits (Asic) Rtl Design Microarchitecture Serial Protocols (Show More) Universal Asynchronous Receiver/transmitter (Uart) I2c Rtl Coding Amba Ahb Dft Amba Joint Test Action Group (Jtag) Lint Cdc Digital Logic Design Field-programmable Gate Arrays (Fpga) Xilinx Vivado Vhdl Static Timing Analysis
Samsung Semiconductor Bengaluru	Staff Engineer - GPU RTL Design Female	6yrs	Base: ₹20.2lakhs Stocks: - Bonus: ₹13.8lakhs CTC:₹34.0lakhs	National Institute of Technology	Formal Property Verification Ptpx Power Artist Microarchitecture Gpu Graphics Processing Unit (Show More) Real Intent Cdc Synopsys Primetime Cadence Verdi Static Timing Analysis Cdc Synthesis Constraints Rtl Design Logic Design Rtl And Netlist Linting (Ascent Lint) Conformal Lec Synthesis (Dc) Cadence Virtuoso Xilinx Ise Micro-cap
Salesforce Bengaluru	Lead Member Of Technical Staff	13.9yrs	Base: ₹88.1lakhs Stocks: ₹39.8lakhs (Today) (4.5%) ₹41.6L Bonus: ₹12.8lakhs CTC:₹140.7lakhs (Today) (1.3%) ₹142.5L	Nanyang Technological University Singapore Indian Institute of Technology (Indian School of Mines)	C Matlab Data Structures Algorithms Simulink Ti Dsps (Show More) Tcl Unix Static Timing Analysis Eda Verilog Programming Digital Signal Processing Optimization Fpga Asic C++ Machine Learning Simulations Vhdl Python Digital Signal Processors Computer Science
Centre for Development of Telematics (C-DOT) Bengaluru	Digital Design Engineer (Scientist B)	1.9yrs	Base: ₹10.1lakhs Stocks: - Bonus: - CTC:₹10.1lakhs	Indian Institute of Technology Hyderabad (IIT-H) Institute of Engineering & Technology DAVV	System On A Chip (Soc) Modelsim Lattice Diamond Software Cadence Schematic Capture Analog Layout Keysight Ads (Show More) Oops Hyperlynx Power Hyperlynx Signal Integrity Cadence Pcb Designer C++ C Assertions Based Verification Systemverilog Cadence Allegro Verilog Cadence Virtuoso Xilinx Vivado Comsol Ltspice Asitic Clewin Constraints Rtl Design CDC Synchonizers Static Timing Analysis I2C SPI Uart FIFO CORDIC
Texas Instruments Bengaluru	Analog Design Engineer (24)	1.7yrs	Base: ₹20.4lakhs Stocks: ₹2.0lakhs (Today) (0.0%) ₹2.0L Bonus: ₹4.1lakhs CTC:₹26.5lakhs (Today) (0.0%) ₹26.5L	Indian Institute of Technology Kharagpur	Design Engineering Mixed-signal Ic Design Integrated Circuits (Ic) Power Management Hardware Design Layout Design (Show More) Schematic Layout Versus Schematic (Lvs) Electronic Engineering Design Rule Checking (Drc) Problem Solving Electrical Engineering Communication Circuits Analog Circuit Design Analog Cadence Virtuoso Verilog Analog Signal Processing Analog Integrated Circuit Design Mixed-signal Integrated Circuits Digital Ic Design Static Timing Analysis Python
Intel Corporation Bengaluru	SoC Architect Male	8yrs		The University of Texas at Austin Delhi Technological University (Formerly DCE)	X86 System On A Chip (Soc) Interconnect Manageability System Architecture Ucie (Show More) Pcie Hardware Design Cache Coherency Operating Systems Python Machine Learning Axi Amba Ahb Apb Logic Synthesis Physical Design Dft Rtl Design Cdc Verilog Systemverilog Rdc Lint Arm Cortex-m Arm Architecture Functional Safety Iso 26262 Advanced Driver-assistance Systems (Adas) Requirements Traceability Microarchitecture Vlsi Cmos Vhdl Static Timing Analysis Embedded Systems C Robotics Matlab Image Processing Html 5 Css3 Javascript Html C++
Texas Instruments Bengaluru	Digital Design Engineer (26)	3.8yrs	Base: ₹28.5lakhs Stocks: - Bonus: ₹4.4lakhs CTC:₹32.9lakhs	Government College of Technology Kongu Polytechnic College	Area Optimization Voltus Microarchitecture Tcsh Universal Verification Methodology (Uvm) Test Planning (Show More) Assertion Based Verification Field-programmable Gate Arrays (Fpga) Simvision Tempus Cadence Virtuoso Physical Design Innovus Genus Conformal Jasper Gold Python Xcelium Vim Bash Digital Circuit Design Rtl Design Conformal Lec Computer Hardware Troubleshooting Verilog Hdl Perl Git Linux Centos Windows Computer Hardware C Microsoft Word Microsoft Excel Microsoft Powerpoint Systemverilog Upf Tcl Modelsim Circuit Analysis Computer Hardware Assembly Computer Hardware Installation Rtl Coding Logic Synthesis Cdc Lint Static Timing Analysis Low-power Design Application-specific Integrated Circuits (Asic) Computer Architecture System On A Chip (Soc) Finite State Machines Rtl-to-gdsii Flow Formal Verification
Texas Instruments Bengaluru	Digital Design Engineer	3.7yrs	Base: ₹28.5lakhs Stocks: - Bonus: ₹4.4lakhs CTC:₹32.9lakhs	Government College of Technology Kongu Polytechnic College	Area Optimization Voltus Microarchitecture Tcsh Universal Verification Methodology (Uvm) Test Planning (Show More) Assertion Based Verification Field-programmable Gate Arrays (Fpga) Simvision Tempus Cadence Virtuoso Physical Design Innovus Genus Conformal Jasper Gold Python Xcelium Vim Bash Digital Circuit Design Rtl Design Conformal Lec Computer Hardware Troubleshooting Verilog Hdl Perl Git Linux Centos Windows Computer Hardware C Microsoft Word Microsoft Excel Microsoft Powerpoint Systemverilog Upf Tcl Modelsim Circuit Analysis Computer Hardware Assembly Computer Hardware Installation Rtl Coding Logic Synthesis Cdc Lint Static Timing Analysis Low-power Design Application-specific Integrated Circuits (Asic) Computer Architecture System On A Chip (Soc) Finite State Machines Rtl-to-gdsii Flow Formal Verification
Qualcomm Bengaluru	Senior Lead Engineer Male	11yrs	Base: ₹38.1lakhs Stocks: ₹15.0lakhs Bonus: ₹4.3lakhs CTC:₹57.4lakhs	Birla Institute of Technology and Science NITTE MEENAKSHI INSTITUTE OF TECHNOLOGY	VLSI CMOS Circuit Design GPIO Cadence Virtuoso SPICE (Show More) Spectre Verilog ASIC Logic Design Characterization Hspice Finesim Xa Embedded Systems Matlab Perl Very-Large-Scale Integration (VLSI) Analog Design Static Timing Analysis Shell

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Frequently asked questions

How much do Static Timing Analysis Bengaluru employees make?

Employees who know Static Timing Analysis in Bengaluru earn an average of ₹34.8lakhs, mostly ranging from ₹16.8lakhs per year to ₹139.1lakhs per year based on 31 profiles. The top 10% of employees earn more than ₹65.5lakhs per year.

What is the average salary of Static Timing Analysis Bengaluru?

Average salary of an employee who know Static Timing Analysis in Bengaluru is ₹34.8lakhs.

What is the highest salary offered who know Static Timing Analysis in Bengaluru?

Highest reported salary offered who know Static Timing Analysis in Bengaluru is ₹140.7lakhs. The top 10% of employees earn more than ₹65.5lakhs per year. The top 1% earn more than a whopping ₹139.1lakhs per year.

What are the most common skills required who know Static Timing Analysis in Bengaluru?

100% of employees have skills in static timing analysis . 0% also know verilog . 0% also know c .

What are the highest paying jobs who know Static Timing Analysis in Bengaluru?

The top 5 highest paying jobs who know Static Timing Analysis in Bengaluru with reported salaries are:

lead member of technical staff - ₹138.0lakhs per year
staff engineer - ₹48.0lakhs per year
analog design engineer - ₹31.0lakhs per year
digital design engineer - ₹27.0lakhs per year
senior engineer - ₹20.0lakhs per year

What is the median salary offered who know Static Timing Analysis in Bengaluru?

The median salary approximately calculated from salary profiles measured so far is ₹24.0lakhs per year.

How is the age distributed among employees who know Static Timing Analysis in Bengaluru?

45% of employees lie between 26-31 yrs . 35% of the employees fall in the age group of 31-36 yrs .

What qualifications do employees have who know Static Timing Analysis in Bengaluru?

23% hold a PostGraduate degree. 12% hold a Graduate degree.

Which schools do employees working who know Static Timing Analysis in Bengaluru went to?

6% of employees studied at Government College of Technology . 6% studied at Indian Institute of Technology (IIT) .

Frequently asked questions

How much do Static Timing Analysis Bengaluru employees make?

What is the average salary of Static Timing Analysis Bengaluru?

Average salary of an employee who know Static Timing Analysis in Bengaluru is ₹34.8lakhs.

What is the highest salary offered who know Static Timing Analysis in Bengaluru?

What are the most common skills required who know Static Timing Analysis in Bengaluru?

100% of employees have skills in static timing analysis . 0% also know verilog . 0% also know c .

What are the highest paying jobs who know Static Timing Analysis in Bengaluru?

The top 5 highest paying jobs who know Static Timing Analysis in Bengaluru with reported salaries are:

lead member of technical staff - ₹138.0lakhs per year
staff engineer - ₹48.0lakhs per year
analog design engineer - ₹31.0lakhs per year
digital design engineer - ₹27.0lakhs per year
senior engineer - ₹20.0lakhs per year

What is the median salary offered who know Static Timing Analysis in Bengaluru?

The median salary approximately calculated from salary profiles measured so far is ₹24.0lakhs per year.

How is the age distributed among employees who know Static Timing Analysis in Bengaluru?

45% of employees lie between 26-31 yrs . 35% of the employees fall in the age group of 31-36 yrs .

What qualifications do employees have who know Static Timing Analysis in Bengaluru?

23% hold a PostGraduate degree. 12% hold a Graduate degree.

Which schools do employees working who know Static Timing Analysis in Bengaluru went to?

6% of employees studied at Government College of Technology . 6% studied at Indian Institute of Technology (IIT) .

Salary Brackets

Percentage
10-20 lakhs	10-20 lakhs Percentage : 42
20-30 lakhs	20-30 lakhs Percentage : 19
30-40 lakhs	30-40 lakhs Percentage : 19
> 50 lakhs	> 50 lakhs Percentage : 19

Age Brackets

Percentage
21-26 yrs	21-26 yrs Percentage : 13
26-31 yrs	26-31 yrs Percentage : 45
31-36 yrs	31-36 yrs Percentage : 35
36-41 yrs	36-41 yrs Percentage : 3
> 41 yrs	> 41 yrs Percentage : 3

Skills

Trending

static timing analysis

100 %

verilog

0 %

rtl design

0 %

vhdl

0 %

c++

0 %

cadence virtuoso

0 %

Schools

Top

Government College of Technology

6 %

Indian Institute of Technology (IIT)

6 %

Indian Institute of Technology (Indian School of Mines)

6 %

Jawaharlal Nehru Technological University (JNTU)

6 %

Kongu Polytechnic College

6 %

Nanyang Technological University Singapore

6 %

St. Xavier's

6 %

Static Timing Analysis Bengaluru Salaries

Average salary is ₹34.8lakhs.

Similar Searches

How much do Static Timing Analysis Bengaluru employees make?

What is the average salary of Static Timing Analysis Bengaluru?

What is the highest salary offered who know Static Timing Analysis in Bengaluru?

What are the most common skills required who know Static Timing Analysis in Bengaluru?

What are the highest paying jobs who know Static Timing Analysis in Bengaluru?

What is the median salary offered who know Static Timing Analysis in Bengaluru?

How is the age distributed among employees who know Static Timing Analysis in Bengaluru?

What qualifications do employees have who know Static Timing Analysis in Bengaluru?

Which schools do employees working who know Static Timing Analysis in Bengaluru went to?

How much do Static Timing Analysis Bengaluru employees make?

What is the average salary of Static Timing Analysis Bengaluru?

What is the highest salary offered who know Static Timing Analysis in Bengaluru?

What are the most common skills required who know Static Timing Analysis in Bengaluru?

What are the highest paying jobs who know Static Timing Analysis in Bengaluru?

What is the median salary offered who know Static Timing Analysis in Bengaluru?

How is the age distributed among employees who know Static Timing Analysis in Bengaluru?

What qualifications do employees have who know Static Timing Analysis in Bengaluru?

Which schools do employees working who know Static Timing Analysis in Bengaluru went to?

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