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Static Timing Analysis Bengaluru Salaries

26 verified profiles

Last updated on December 21, 2024

Average salary is ₹30.4lakhs.

Employees who know Static Timing Analysis in Bengaluru earn an average of ₹30.4lakhs, mostly ranging from ₹16.5lakhs to ₹118.8lakhs based on 26 profiles.

👨‍💻 Male	₹25lakhs Male Average Salary : ₹ 25 lakhs
👩‍💻 Female	₹18lakhs Female Average Salary : ₹ 18 lakhs

For every ₹100 paid to men, women are paid ₹72

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Salary Profiles

Company	Title	Experience	Annual Salary	School	Skills
Texas Instruments Bengaluru	Analog Design Engineer (24)	1.7yrs	Base: ₹20.4lakhs Stocks: ₹2.0lakhs Bonus: ₹4.1lakhs CTC:₹26.5lakhs	Indian Institute of Technology Kharagpur	Design Engineering Mixed-signal Ic Design Integrated Circuits (Ic) Power Management Hardware Design Layout Design (Show More) Schematic Layout Versus Schematic (Lvs) Electronic Engineering Design Rule Checking (Drc) Problem Solving Electrical Engineering Communication Circuits Analog Circuit Design Analog Cadence Virtuoso Verilog Analog Signal Processing Analog Integrated Circuit Design Mixed-signal Integrated Circuits Digital Ic Design Static Timing Analysis Python
Texas Instruments Bengaluru	Digital Design Engineer	4.1yrs	Base: ₹28.5lakhs Stocks: - Bonus: ₹4.4lakhs CTC:₹32.9lakhs	Government College of Technology Kongu Polytechnic College	Power Analysis Area Optimization Voltus Microarchitecture Tcsh Universal Verification Methodology (Uvm) (Show More) Test Planning Assertion Based Verification Field-programmable Gate Arrays (Fpga) Simvision Tempus Cadence Virtuoso Physical Design Innovus Genus Conformal Jasper Gold Python Xcelium Vim Bash Digital Circuit Design Rtl Design Conformal Lec Computer Hardware Troubleshooting Verilog Hdl Perl Git Linux Centos Windows Computer Hardware C Microsoft Word Microsoft Excel Microsoft Powerpoint Systemverilog Upf Tcl Modelsim Circuit Analysis Computer Hardware Assembly Computer Hardware Installation Rtl Coding Logic Synthesis Cdc Lint Static Timing Analysis Low-power Design Application-specific Integrated Circuits (Asic) Computer Architecture System On A Chip (Soc) Finite State Machines Rtl-to-gdsii Flow Formal Verification
Intel Corporation Bengaluru	SoC Architect Male	8yrs		The University of Texas at Austin Delhi Technological University (Formerly DCE)	X86 System On A Chip (Soc) Interconnect Manageability System Architecture Ucie (Show More) Pcie Hardware Design Cache Coherency Operating Systems Python Machine Learning Axi Amba Ahb Apb Logic Synthesis Physical Design Dft Rtl Design Cdc Verilog Systemverilog Rdc Lint Arm Cortex-m Arm Architecture Functional Safety Iso 26262 Advanced Driver-assistance Systems (Adas) Requirements Traceability Microarchitecture Vlsi Cmos Vhdl Static Timing Analysis Embedded Systems C Robotics Matlab Image Processing Html 5 Css3 Javascript Html C++
Salesforce Bengaluru	Lead Member Of Technical Staff	13.1yrs	Base: ₹82.9lakhs Stocks: ₹39.8lakhs Bonus: ₹12.8lakhs CTC:₹135.5lakhs	Nanyang Technological University Singapore Indian Institute of Technology (Indian School of Mines)	Algorithms Programming C Computer Science Distributed Systems Data Structures (Show More) Digital Signal Processors Matlab C++ Unix Mysql Docker Java Nosql Angularjs2 Amazon Web Services (Aws) Simulink Spring Framework Terraform Javaserver Pages (Jsp) Digital Signal Processing Ti Dsps Amazon Dynamodb Static Timing Analysis Redis Eda Couchbase Rabbitmq Kubernetes Apache Kafka Golang
Texas Instruments Bengaluru	Digital Design Engineer (26)	3.8yrs	Base: ₹28.5lakhs Stocks: - Bonus: ₹4.4lakhs CTC:₹32.9lakhs	Government College of Technology Kongu Polytechnic College	Area Optimization Voltus Microarchitecture Tcsh Universal Verification Methodology (Uvm) Test Planning (Show More) Assertion Based Verification Field-programmable Gate Arrays (Fpga) Simvision Tempus Cadence Virtuoso Physical Design Innovus Genus Conformal Jasper Gold Python Xcelium Vim Bash Digital Circuit Design Rtl Design Conformal Lec Computer Hardware Troubleshooting Verilog Hdl Perl Git Linux Centos Windows Computer Hardware C Microsoft Word Microsoft Excel Microsoft Powerpoint Systemverilog Upf Tcl Modelsim Circuit Analysis Computer Hardware Assembly Computer Hardware Installation Rtl Coding Logic Synthesis Cdc Lint Static Timing Analysis Low-power Design Application-specific Integrated Circuits (Asic) Computer Architecture System On A Chip (Soc) Finite State Machines Rtl-to-gdsii Flow Formal Verification
Texas Instruments Bengaluru	Digital Design Engineer	3.7yrs	Base: ₹28.5lakhs Stocks: - Bonus: ₹4.4lakhs CTC:₹32.9lakhs	Government College of Technology Kongu Polytechnic College	Area Optimization Voltus Microarchitecture Tcsh Universal Verification Methodology (Uvm) Test Planning (Show More) Assertion Based Verification Field-programmable Gate Arrays (Fpga) Simvision Tempus Cadence Virtuoso Physical Design Innovus Genus Conformal Jasper Gold Python Xcelium Vim Bash Digital Circuit Design Rtl Design Conformal Lec Computer Hardware Troubleshooting Verilog Hdl Perl Git Linux Centos Windows Computer Hardware C Microsoft Word Microsoft Excel Microsoft Powerpoint Systemverilog Upf Tcl Modelsim Circuit Analysis Computer Hardware Assembly Computer Hardware Installation Rtl Coding Logic Synthesis Cdc Lint Static Timing Analysis Low-power Design Application-specific Integrated Circuits (Asic) Computer Architecture System On A Chip (Soc) Finite State Machines Rtl-to-gdsii Flow Formal Verification
Qualcomm Bengaluru	Senior Lead Engineer Male	11yrs		Birla Institute of Technology and Science NITTE MEENAKSHI INSTITUTE OF TECHNOLOGY	VLSI CMOS Circuit Design GPIO Cadence Virtuoso SPICE (Show More) Spectre Verilog ASIC Logic Design Characterization Hspice Finesim Xa Embedded Systems Matlab Perl Very-Large-Scale Integration (VLSI) Analog Design Static Timing Analysis Shell
Wipro Technologies Bangalore	Physical Design Engineer (2) Male	3.9yrs	Base: ₹11.8lakhs Stocks: - Bonus: - CTC:₹11.8lakhs	Visvesvaraya Technological University	Static Timing Analysis Physical Design
Cerium Systems Bengaluru	Senior Engineer - RTL Design Male	6.1yrs	Base: ₹15.3lakhs Stocks: - Bonus: - CTC:₹15.3lakhs	Jalpaiguri Government Engineering College	Unix C Perl Verilog Rtl Design And Verifiaction C++ Microsoft Office (Show More) Microsoft Excel Microsoft Word Microsoft Powerpoint Tcl-tk System Verilog For Verification Static Timing Analysis Verilog Tk Systemverilog Genus Hal Python Artificial Intelligence (Ai) C
AMD Bengaluru	Silicon Design Engineer II Female	3.1yrs	Base: ₹17.0lakhs Stocks: ₹4.3lakhs Bonus: ₹1.3lakhs CTC:₹22.6lakhs	Dr. A.P.J. Abdul Kalam Technical University	Object-oriented Programming (Oop) Functional Verification Universal Verification Methodology (Uvm) System Verilog Pss Verilog (Show More) System On A Chip (Soc) Axi C++ X86 Computer Architecture Static Timing Analysis Design Vhdl Electronic Circuit Design Shell Scripting Debugging Verdi Palladium Xcelium

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Frequently asked questions

How much do Static Timing Analysis Bengaluru employees make?

Employees who know Static Timing Analysis in Bengaluru earn an average of ₹30.4lakhs, mostly ranging from ₹16.5lakhs per year to ₹118.8lakhs per year based on 26 profiles. The top 10% of employees earn more than ₹58.8lakhs per year.

What is the average salary of Static Timing Analysis Bengaluru?

Average salary of an employee who know Static Timing Analysis in Bengaluru is ₹30.4lakhs.

What is the highest salary offered who know Static Timing Analysis in Bengaluru?

Highest reported salary offered who know Static Timing Analysis in Bengaluru is ₹135.5lakhs. The top 10% of employees earn more than ₹58.8lakhs per year. The top 1% earn more than a whopping ₹118.8lakhs per year.

What are the most common skills required who know Static Timing Analysis in Bengaluru?

100% of employees have skills in static timing analysis . 0% also know verilog . 0% also know perl .

What are the highest paying jobs who know Static Timing Analysis in Bengaluru?

The top 5 highest paying jobs who know Static Timing Analysis in Bengaluru with reported salaries are:

digital design engineer - ₹33.0lakhs per year
senior engineer - ₹20.0lakhs per year
senior design engineer - ₹16.0lakhs per year
senior fpga design engineer - ₹15.0lakhs per year
physical design engineer - ₹14.0lakhs per year

What is the median salary offered who know Static Timing Analysis in Bengaluru?

The median salary approximately calculated from salary profiles measured so far is ₹21.8lakhs per year.

How is the age distributed among employees who know Static Timing Analysis in Bengaluru?

42% of employees lie between 26-31 yrs . 35% of the employees fall in the age group of 31-36 yrs .

What qualifications do employees have who know Static Timing Analysis in Bengaluru?

27% hold a PostGraduate degree. 11% hold a Graduate degree.

Which schools do employees working who know Static Timing Analysis in Bengaluru went to?

12% of employees studied at Government College of Technology . 12% studied at Kongu Polytechnic College .

Frequently asked questions

How much do Static Timing Analysis Bengaluru employees make?

What is the average salary of Static Timing Analysis Bengaluru?

Average salary of an employee who know Static Timing Analysis in Bengaluru is ₹30.4lakhs.

What is the highest salary offered who know Static Timing Analysis in Bengaluru?

What are the most common skills required who know Static Timing Analysis in Bengaluru?

100% of employees have skills in static timing analysis . 0% also know verilog . 0% also know perl .

What are the highest paying jobs who know Static Timing Analysis in Bengaluru?

The top 5 highest paying jobs who know Static Timing Analysis in Bengaluru with reported salaries are:

digital design engineer - ₹33.0lakhs per year
senior engineer - ₹20.0lakhs per year
senior design engineer - ₹16.0lakhs per year
senior fpga design engineer - ₹15.0lakhs per year
physical design engineer - ₹14.0lakhs per year

What is the median salary offered who know Static Timing Analysis in Bengaluru?

The median salary approximately calculated from salary profiles measured so far is ₹21.8lakhs per year.

How is the age distributed among employees who know Static Timing Analysis in Bengaluru?

42% of employees lie between 26-31 yrs . 35% of the employees fall in the age group of 31-36 yrs .

What qualifications do employees have who know Static Timing Analysis in Bengaluru?

27% hold a PostGraduate degree. 11% hold a Graduate degree.

Which schools do employees working who know Static Timing Analysis in Bengaluru went to?

12% of employees studied at Government College of Technology . 12% studied at Kongu Polytechnic College .

Salary Brackets

Percentage
10-20 lakhs	10-20 lakhs Percentage : 46
20-30 lakhs	20-30 lakhs Percentage : 23
30-40 lakhs	30-40 lakhs Percentage : 15
> 50 lakhs	> 50 lakhs Percentage : 15

Age Brackets

Percentage
21-26 yrs	21-26 yrs Percentage : 15
26-31 yrs	26-31 yrs Percentage : 42
31-36 yrs	31-36 yrs Percentage : 35
36-41 yrs	36-41 yrs Percentage : 4
> 41 yrs	> 41 yrs Percentage : 4

Skills

Trending

static timing analysis

100 %

verilog

0 %

perl

0 %

c++

0 %

cadence virtuoso

0 %

modelsim

0 %

Schools

Top

Government College of Technology

12 %

Kongu Polytechnic College

12 %

Indian Institute of Technology (IIT)

8 %

Jawaharlal Nehru Technological University (JNTU)

8 %

St. Xavier's

8 %

Visveswaraiah Technological University (VTU)

8 %

bit mesra

8 %

Static Timing Analysis Bengaluru Salaries

Average salary is ₹30.4lakhs.

Similar Searches

How much do Static Timing Analysis Bengaluru employees make?

What is the average salary of Static Timing Analysis Bengaluru?

What is the highest salary offered who know Static Timing Analysis in Bengaluru?

What are the most common skills required who know Static Timing Analysis in Bengaluru?

What are the highest paying jobs who know Static Timing Analysis in Bengaluru?

What is the median salary offered who know Static Timing Analysis in Bengaluru?

How is the age distributed among employees who know Static Timing Analysis in Bengaluru?

What qualifications do employees have who know Static Timing Analysis in Bengaluru?

Which schools do employees working who know Static Timing Analysis in Bengaluru went to?

How much do Static Timing Analysis Bengaluru employees make?

What is the average salary of Static Timing Analysis Bengaluru?

What is the highest salary offered who know Static Timing Analysis in Bengaluru?

What are the most common skills required who know Static Timing Analysis in Bengaluru?

What are the highest paying jobs who know Static Timing Analysis in Bengaluru?

What is the median salary offered who know Static Timing Analysis in Bengaluru?

How is the age distributed among employees who know Static Timing Analysis in Bengaluru?

What qualifications do employees have who know Static Timing Analysis in Bengaluru?

Which schools do employees working who know Static Timing Analysis in Bengaluru went to?

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