Company	Title	Experience	Annual Salary	School	Skills
Intel Hyderabad	SoC Design and Validation Intern	2yrs	Base: ₹16.1lakhs Stocks: ₹3.9lakhs (Today) (12.8%) ₹4.4L Bonus: ₹3.9lakhs CTC:₹23.9lakhs (Today) (2.1%) ₹24.4L	University of Hyderabad University College of Engineering	Ip Development System Requirements Hardware Development Axi Amba Scripting (Show More) Design Development Semiconductor Fabrication Arm Architecture Hardware Architecture Risc-v Design Electrical Engineering Semiconductor Engineering Mixed-signal Integrated Circuits Performance Analysis System Integration Hardware Design Computer Arithmetic Low-power Design
AMD Hyderabad	Silicon design engineer2	6yrs	Base: ₹23.5lakhs Stocks: ₹10.1lakhs (Today) (48.5%) ₹15.0L Bonus: ₹3.4lakhs CTC:₹37.0lakhs (Today) (13.2%) ₹41.9L	Krishna chaitanya Institute of Technology & Sciences	Workload Prioritization Task Management Agile Methodologies Code Coverage Microsoft Excel Microsoft Powerpoint (Show More) Jira Functional Verification Risc-v Universal Verification Methodology (Uvm) System Verilog Verilog Very-large-scale Integration (Vlsi) C Microsoft Office Matlab Vhdl Cmos Systemverilog
Qualcomm Noida	Senior Design Engineer	4.3yrs		Indian Institute of Technology Sardar Patel Vidyalaya	Risc-v Arm Architecture Systemverilog Amba Microarc Lint (Show More) Cache Coherency Spyglass Performance Analysis Coverage Analysis Digital Designs Communication Design Engineering Computer-aided Design (Cad) Electrical Engineering C++ Machine Learning Computer Architecture Android Development Python C Computer Vision System Verilog Matlab Java Verilog Algorithms Computer Science Artificial Intelligence (Ai) Rtl Design Perl Shell Scripting Perl Automation Object Oriented Perl Amba Ahb Csh Synopsys Tools
Siemens EDA (Siemens Digital Industries Software) Noida	Lead Member Technical Staff (T08)	5.9yrs	Base: ₹30.2lakhs Stocks: ₹5.0lakhs Bonus: ₹5.9lakhs CTC:₹41.1lakhs	Manav Rachna University DAV Public School	Universal Verification Methodology (Uvm) Systemverilog Hardware Verification C Python Object-oriented Programming (Oop) (Show More) Verilog Application-specific Integrated Circuits (Asic) Functional Verification Linux Git Displayport 2.0 Amba Axi Amba Axistream Amba Apb Tilelink Amba Ahb Risc-v I2c Mipi Dsi2 Usb3.0 Tanner Eda Tcl Vhdl Bash Microsoft Office Matlab .Net Framework Labview
AMD Hyderabad	Member of Technical Staff Male	9.7yrs	Base: ₹36.7lakhs Stocks: ₹8.7lakhs (Today) (14.9%) ₹10.0L Bonus: ₹1.9lakhs CTC:₹47.3lakhs (Today) (2.7%) ₹48.6L	Jawaharlal Nehru Technological University	System On A Chip (Soc) Universal Verification Methodology (Uvm) Perl Field-programmable Gate Arrays (Fpga) Application-specific Integrated Circuits (Asic) Digital Electronics (Show More) Very-large-scale Integration (Vlsi) C C++ Linux Verilog Vhdl Problem Solving Communication Systemverilog Open Verification Methodology Axi Ahb Synopsys Vcs Makefile Sv Power Management Apb Written Communication Python Debugging Functional Verification Semiconductors Risc-v Tilelink Wit Git Chisel Scala Object-oriented Programming (Oop) Microsoft Office Microsoft Excel Microsoft Powerpoint Microsoft Outlook Machine Learning
NXP Semiconductors Noida	Senior Design Engineer	4.2yrs		Indian Institute of Technology Sardar Patel Vidyalaya	Risc-v Arm Architecture Systemverilog Amba Microarc Lint (Show More) Cache Coherency Spyglass Performance Analysis Coverage Analysis Digital Designs Communication Design Engineering Computer-aided Design (Cad) Electrical Engineering C++ Machine Learning Computer Architecture Android Development Python C Computer Vision System Verilog Matlab Java Verilog Algorithms Computer Science Artificial Intelligence (Ai) Rtl Design Perl Shell Scripting Perl Automation Object Oriented Perl Amba Ahb Csh Synopsys Tools
EdgeQ Inc. Bengaluru	Member Of Technical Staff	2.9yrs	Base: ₹20.6lakhs Stocks: ₹1.3lakhs Bonus: - CTC:₹21.9lakhs	Motilal Nehru Institute National Institute of Technology	Verilog C System Verilog Asic Uvm Debugging (Show More) Tcl she Shell Scripting Makefile Risc-v Ethernet
SiFive Bengaluru	Staff Engineer	8.8yrs		College of Engineering Trivandrum	Scripting Logic Design Automation Project Management Rtl Design Fpga Prototyping (Show More) Embedded Systems C Bluetooth Low Energy Can Protocol Python Linux Robotics Lidar Microcontrollers Msp430 Atmel Avr C++ Digital Circuit Design Arduino Qt Raspberry Pi Rapid Prototyping Jenkins Nrf Embedded Linux Stm Git Clearcase Real-time Operating Systems (Rtos) Embedded C Arm Architecture Engineering Microsoft Office Field-programmable Gate Arrays (Fpga) Verilog Wireless Mesh Internet Of Things (Iot) Javascript Node.js Fw Troubleshooting Embedded Software Arm Cortex-m Prototyping Application-specific Integrated Circuits (Asic) System On A Chip (Soc) Risc-v
Eloelo Bengaluru	Software Engineer	1.6yrs	Base: ₹15.7lakhs Stocks: - Bonus: ₹1.0lakhs CTC:₹16.7lakhs		Amazon Web Services (Aws) Redis Software Infrastructure Spring Boot Software Development Java (Show More) Python Apache Kafka Elasticsearch Risc-v Flask Rest Apis Computer Vision Kotlin Android Development Google Maps Api Reasoning Skills Back-end Web Development Databases Computer Science Design Systems Software Design Programming Google Cloud Platform (Gcp) Product Design Problem Solving Scikit-learn Opencv Cloud Firestore Firebase Mongodb Postgresql Database Management System (Dbms) Hive Html Object-oriented Programming (Oop) Git C++ Research Engineering Strategy Analytical Skills Data Structures Algorithms Sql

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Frequently asked questions

How much do Risc-v employees make?

Employees who know Risc-v earn an average of ₹37.3lakhs, mostly ranging from ₹34.4lakhs per year to ₹50.6lakhs per year based on 9 profiles. The top 10% of employees earn more than ₹48.7lakhs per year.

What is the average salary of Risc-v?

Average salary of an employee who know Risc-v is ₹37.3lakhs.

What is the median salary offered who know Risc-v?

The median salary approximately calculated from salary profiles measured so far is ₹41.1lakhs per year.

How is the age distributed among employees who know Risc-v?

44% of employees lie between 26-31 yrs . 33% of the employees fall in the age group of 21-26 yrs .

Frequently asked questions

How much do Risc-v employees make?

What is the average salary of Risc-v?

Average salary of an employee who know Risc-v is ₹37.3lakhs.

What is the median salary offered who know Risc-v?

The median salary approximately calculated from salary profiles measured so far is ₹41.1lakhs per year.

How is the age distributed among employees who know Risc-v?

44% of employees lie between 26-31 yrs . 33% of the employees fall in the age group of 21-26 yrs .

Salary Brackets

Percentage
10-20 lakhs	10-20 lakhs Percentage : 11
20-30 lakhs	20-30 lakhs Percentage : 22
30-40 lakhs	30-40 lakhs Percentage : 11
40-50 lakhs	40-50 lakhs Percentage : 44
> 50 lakhs	> 50 lakhs Percentage : 11

Age Brackets

Percentage
21-26 yrs	21-26 yrs Percentage : 33
26-31 yrs	26-31 yrs Percentage : 44
31-36 yrs	31-36 yrs Percentage : 11

Skills

Trending

risc v

100 %

0 %

verilog

0 %

python

0 %

c++

0 %

systemverilog

0 %

arm architecture

0 %

Schools

Top

Indian Institute of Technology

22 %

Sardar Patel Vidyalaya

22 %

College of Engineering Trivandrum

11 %

DAV Public School

11 %

Jawaharlal Nehru Technological University

11 %

Krishna chaitanya Institute of Technology & Sciences

11 %

Manav Rachna University

11 %

Risc-v Salaries

Average salary is ₹37.3lakhs.

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What is the average salary of Risc-v?

What is the median salary offered who know Risc-v?

How is the age distributed among employees who know Risc-v?

How much do Risc-v employees make?

What is the average salary of Risc-v?

What is the median salary offered who know Risc-v?

How is the age distributed among employees who know Risc-v?

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