Company	Title	Experience	Annual Salary	School	Skills
Marvel Technologies Pune	Senior Staff Engineer (t4)	13.3yrs		Sinhgad College of Engineering	System Verilog Verilog OVM SystemVerilog ASIC Open Verification Methodology (Show More) VLSI VHDL AMBA Embedded Systems Semiconductors Xilinx Compilers USB3.0 Functional Verification SoC RTL coding ModelSim Static Timing Analysis AMBA AHB TCL Debugging RTL design FPGA Veritas Cluster Server NCSim USB EDA RTL Design
AMD Hyderabad	Member of Technical Staff Male	9.7yrs	Base: ₹36.7lakhs Stocks: ₹8.7lakhs (Today) (108.0%) ₹18.1L Bonus: ₹1.9lakhs CTC:₹47.3lakhs (Today) (19.9%) ₹56.7L	Jawaharlal Nehru Technological University	System On A Chip (Soc) Universal Verification Methodology (Uvm) Perl Field-programmable Gate Arrays (Fpga) Application-specific Integrated Circuits (Asic) Digital Electronics (Show More) Very-large-scale Integration (Vlsi) C C++ Linux Verilog Vhdl Problem Solving Communication Systemverilog Open Verification Methodology Axi Ahb Synopsys Vcs Makefile Sv Power Management Apb Written Communication Python Debugging Functional Verification Semiconductors Risc-v Tilelink Wit Git Chisel Scala Object-oriented Programming (Oop) Microsoft Office Microsoft Excel Microsoft Powerpoint Microsoft Outlook Machine Learning
Intel Santa Clara	Staff Engineer Male	16.3yrs		Indian Institute of Technology P.g. College of Law	Functional Verification Formal Verification Eda Systemverilog Perl Low Power Design (Show More) Tcl Soc Logic Synthesis Vlsi Asic Rtl Design Power Management Semiconductors Cadence Debugging Verilog Static Timing Analysis Cad Vhdl Physical Design Embedded Systems Open Verification Methodology Integrated Circuit Design Rtl Coding Amba Ahb Usb Analog Arm Timing Closure Modelsim Primetime Fpga Ncsim Ic Cmos Specman Dft
Intel Corporation Hyderabad	IP Design Verification Engineer (7)	7.6yrs	Base: ₹35.9lakhs Stocks: ₹5.8lakhs (Today) (96.6%) ₹11.4L Bonus: ₹2.9lakhs CTC:₹44.6lakhs (Today) (12.6%) ₹50.2L	Maven Silicon Softech Pvt. Ltd. Nalla Malla Reddy Engineering College	Universal Verification Methodology (Uvm) Verilog C Linux Perl System Verilog (Show More) Ovm Synopsys Vcs Verdi Open Verification Methodology Functional Verification Dve Assertions Assertion Based Verification Digital Electronics Jaspergold Formal Verification Microsoft Excel Microsoft Word Microsoft Office
Intel Corporation Hyderabad	IP Design Verification Engineer	7.3yrs	Base: ₹27.2lakhs Stocks: ₹5.8lakhs (Today) (105.2%) ₹11.9L Bonus: ₹2.9lakhs CTC:₹35.9lakhs (Today) (17.0%) ₹42.0L	Maven Silicon Softech Pvt. Ltd. Nalla Malla Reddy Engineering College	Universal Verification Methodology (Uvm) Verilog C Linux Perl System Verilog (Show More) Ovm Synopsys Vcs Verdi Open Verification Methodology Functional Verification Dve Assertions Assertion Based Verification Digital Electronics Jaspergold Formal Verification Microsoft Excel Microsoft Word Microsoft Office
pmc-sierra india private Bangalore	senior design verification methodology engineer Male	11yrs	CTC:₹23.0lakhs	Anna University College of Engineering	SV Open Verification Methodology UVM CAD Perl

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Frequently asked questions

How much do Open Verification Methodology employees make?

Employees who know Open Verification Methodology earn an average of ₹54.9lakhs, mostly ranging from ₹42.4lakhs per year to ₹106.9lakhs per year based on 6 profiles. The top 10% of employees earn more than ₹87.2lakhs per year.

What is the average salary of Open Verification Methodology?

Average salary of an employee who know Open Verification Methodology is ₹54.9lakhs.

What is the median salary offered who know Open Verification Methodology?

The median salary approximately calculated from salary profiles measured so far is ₹45.9lakhs per year.

How is the age distributed among employees who know Open Verification Methodology?

This group has a predominantly younger workforce. 83% of employees lie between 31-36 yrs . 17% of the employees fall in the age group of 36-41 yrs .

Frequently asked questions

How much do Open Verification Methodology employees make?

What is the average salary of Open Verification Methodology?

Average salary of an employee who know Open Verification Methodology is ₹54.9lakhs.

What is the median salary offered who know Open Verification Methodology?

The median salary approximately calculated from salary profiles measured so far is ₹45.9lakhs per year.

How is the age distributed among employees who know Open Verification Methodology?

This group has a predominantly younger workforce. 83% of employees lie between 31-36 yrs . 17% of the employees fall in the age group of 36-41 yrs .

Salary Brackets

Percentage
20-30 lakhs	20-30 lakhs Percentage : 17
30-40 lakhs	30-40 lakhs Percentage : 17
40-50 lakhs	40-50 lakhs Percentage : 33
> 50 lakhs	> 50 lakhs Percentage : 33

Age Brackets

Percentage
31-36 yrs	31-36 yrs Percentage : 83
36-41 yrs	36-41 yrs Percentage : 17

Skills

Trending

open verification methodology

100 %

functional verification

0 %

perl

0 %

verilog

0 %

debugging

0 %

digital electronics

0 %

Open Verification Methodology Salaries

Average salary is ₹54.9lakhs.

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How much do Open Verification Methodology employees make?

What is the average salary of Open Verification Methodology?

What is the median salary offered who know Open Verification Methodology?

How is the age distributed among employees who know Open Verification Methodology?

How much do Open Verification Methodology employees make?

What is the average salary of Open Verification Methodology?

What is the median salary offered who know Open Verification Methodology?

How is the age distributed among employees who know Open Verification Methodology?

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