Company	Title	Experience	Annual Salary	School	Skills
Samsung Semiconductor Bengaluru	Staff Engineer - GPU RTL Design Female	6yrs	Base: ₹20.2lakhs Stocks: - Bonus: ₹13.8lakhs CTC:₹34.0lakhs	National Institute of Technology	Formal Property Verification Ptpx Power Artist Microarchitecture Gpu Graphics Processing Unit (Show More) Real Intent Cdc Synopsys Primetime Cadence Verdi Static Timing Analysis Cdc Synthesis Constraints Rtl Design Logic Design Rtl And Netlist Linting (Ascent Lint) Conformal Lec Synthesis (Dc) Cadence Virtuoso Xilinx Ise Micro-cap
Titan Company Limited Hyderabad	Software Developer Male	1yrs	Base: ₹10.6lakhs Stocks: - Bonus: ₹1.0lakhs CTC:₹11.6lakhs	Birla Institute of Technology and Science St. Anselm's Pink City Sr. Sec. School	Version Control Json Agile Methodologies Passionate About Work Software Development Devops (Show More) Cloud Computing Representational State Transfer (Rest) Xml Cascading Style Sheets (Css) Html Mysql Nosql Java Development Object-oriented Programming (Oop) React.js Core Java Front-end Development Rdbms Multithreading C++ Spring Boot Microarchitecture Rest Api Restful Webservices Hibernate Junit Algorithms Systems Design Object Oriented Programming Mysql Aws Azure Kafka Git
Texas Instruments Bengaluru	Digital Design Engineer (26)	4.5yrs	Base: ₹35.6lakhs Stocks: ₹4.6lakhs (Today) (10.9%) ₹4.1L Bonus: ₹5.4lakhs CTC:₹45.6lakhs (Today) (1.1%) ₹45.1L	Government College of Technology Kongu Polytechnic College	Rdc Xilinx Vivado Fpga Prototyping Technical Documentation Technical Drawing Rtl Verification (Show More) Universal Asynchronous Receiver/transmitter (Uart) Spi Power Analysis Area Optimization Voltus Microarchitecture Tcsh Universal Verification Methodology (Uvm) Test Planning Assertion Based Verification Field-programmable Gate Arrays (Fpga) Simvision Tempus Cadence Virtuoso
Texas Instruments Bengaluru	Digital Design Engineer	4.6yrs	Base: ₹28.5lakhs Stocks: - Bonus: ₹4.4lakhs CTC:₹32.9lakhs	Government College of Technology Kongu Polytechnic College	Rdc Xilinx Vivado Fpga Prototyping Technical Documentation Technical Drawing Rtl Verification (Show More) Universal Asynchronous Receiver/transmitter (Uart) Spi Power Analysis Area Optimization Voltus Microarchitecture Tcsh Universal Verification Methodology (Uvm) Test Planning Assertion Based Verification Field-programmable Gate Arrays (Fpga) Simvision Tempus Cadence Virtuoso
AMD Hyderabad	Senior Silicon Design Engineer	6.6yrs		Veer Surendra Sai University Of Technology ( Formerly UCE ) Mother's Public School	Axi Microarchitecture Power Management Functional Verification Formal Verification Project Management (Show More) Systemverilog Universal Verification Methodology (Uvm) Application-specific Integrated Circuits (Asic) Research Digital Electronics Electronics Engineering Linux C C++ Management Microsoft Word Leadership Electronics And Telecommunications
Intel Corporation Bengaluru	SoC Architect Male	8yrs		The University of Texas at Austin Delhi Technological University (Formerly DCE)	X86 System On A Chip (Soc) Interconnect Manageability System Architecture Ucie (Show More) Pcie Hardware Design Cache Coherency Operating Systems Python Machine Learning Axi Amba Ahb Apb Logic Synthesis Physical Design Dft Rtl Design Cdc Verilog Systemverilog Rdc Lint Arm Cortex-m Arm Architecture Functional Safety Iso 26262 Advanced Driver-assistance Systems (Adas) Requirements Traceability Microarchitecture Vlsi Cmos Vhdl Static Timing Analysis Embedded Systems C Robotics Matlab Image Processing Html 5 Css3 Javascript Html C++
NxtWave Hyderabad	Head of Product Male	12.1yrs	Base: ₹11.3lakhs Stocks: ₹5.6lakhs Bonus: - CTC:₹16.9lakhs	International Institute of Information Technology Hyderabad (IIITH)	Customer Success Product Management Team Building Verilog Vhdl Xilinx (Show More) C++ Matlab Fpga Embedded Systems Asic C Soc Functional Verification Algorithms Data Structures Vlsi Computer Architecture Multisim Python Atmel Avr Microcontrollers Beagle Board Tanner Verdi Perforce Unix Shell Scripting Logic Design Microarchitecture Usb Ni Multisim Rtl Design Shell Scripting Application-specific Integrated Circuits (Asic) Firmware Wireless Sensor Networks Rapid Prototyping Reverse Engineering Manufacturing Lorawan Lora Internet Of Things (Iot) Hardware Architecture Printed Circuit Board (Pcb) Design Product Development Artificial Intelligence For Business Generative Ai Tools Product Design Product Launch
Texas Instruments Bengaluru	Digital Design Engineer (26)	3.8yrs	Base: ₹28.5lakhs Stocks: - Bonus: ₹4.4lakhs CTC:₹32.9lakhs	Government College of Technology Kongu Polytechnic College	Area Optimization Voltus Microarchitecture Tcsh Universal Verification Methodology (Uvm) Test Planning (Show More) Assertion Based Verification Field-programmable Gate Arrays (Fpga) Simvision Tempus Cadence Virtuoso Physical Design Innovus Genus Conformal Jasper Gold Python Xcelium Vim Bash Digital Circuit Design Rtl Design Conformal Lec Computer Hardware Troubleshooting Verilog Hdl Perl Git Linux Centos Windows Computer Hardware C Microsoft Word Microsoft Excel Microsoft Powerpoint Systemverilog Upf Tcl Modelsim Circuit Analysis Computer Hardware Assembly Computer Hardware Installation Rtl Coding Logic Synthesis Cdc Lint Static Timing Analysis Low-power Design Application-specific Integrated Circuits (Asic) Computer Architecture System On A Chip (Soc) Finite State Machines Rtl-to-gdsii Flow Formal Verification
Texas Instruments Bengaluru	Digital Design Engineer	3.7yrs	Base: ₹28.5lakhs Stocks: - Bonus: ₹4.4lakhs CTC:₹32.9lakhs	Government College of Technology Kongu Polytechnic College	Area Optimization Voltus Microarchitecture Tcsh Universal Verification Methodology (Uvm) Test Planning (Show More) Assertion Based Verification Field-programmable Gate Arrays (Fpga) Simvision Tempus Cadence Virtuoso Physical Design Innovus Genus Conformal Jasper Gold Python Xcelium Vim Bash Digital Circuit Design Rtl Design Conformal Lec Computer Hardware Troubleshooting Verilog Hdl Perl Git Linux Centos Windows Computer Hardware C Microsoft Word Microsoft Excel Microsoft Powerpoint Systemverilog Upf Tcl Modelsim Circuit Analysis Computer Hardware Assembly Computer Hardware Installation Rtl Coding Logic Synthesis Cdc Lint Static Timing Analysis Low-power Design Application-specific Integrated Circuits (Asic) Computer Architecture System On A Chip (Soc) Finite State Machines Rtl-to-gdsii Flow Formal Verification
Cadence Design Systems Bengaluru	Design Engineer II Male	3.4yrs	Base: ₹17.6lakhs Stocks: - Bonus: ₹2.6lakhs CTC:₹20.2lakhs		Test Planning Scripting Hardware Design Problem Solving Microarchitecture Assertion Based Verification (Show More) Formal Verification Embedded C Jasper Sva Usb3.x Ltssm Systemverilog System On A Chip (Soc) Application-specific Integrated Circuits (Asic) Universal Verification Methodology (Uvm) Verilog C Matlab Simulink Xilinx Vivado Ni Labview Arduino Ide Jupyter C++ Python Vhdl Microsoft Office Management Leadership Teamwork English Urdu Hindi Code Composer Studio Systemverilog (Basics) Design Verification Soc Verifiction

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Frequently asked questions

How much do Microarchitecture employees make?

Employees who know Microarchitecture earn an average of ₹33.1lakhs, mostly ranging from ₹26.6lakhs per year to ₹66.7lakhs per year based on 11 profiles. The top 10% of employees earn more than ₹49.3lakhs per year.

What is the average salary of Microarchitecture?

Average salary of an employee who know Microarchitecture is ₹33.1lakhs.

What is the median salary offered who know Microarchitecture?

The median salary approximately calculated from salary profiles measured so far is ₹32.9lakhs per year.

How is the age distributed among employees who know Microarchitecture?

36% of employees lie between 26-31 yrs . 27% of the employees fall in the age group of 21-26 yrs .

Frequently asked questions

How much do Microarchitecture employees make?

What is the average salary of Microarchitecture?

Average salary of an employee who know Microarchitecture is ₹33.1lakhs.

What is the median salary offered who know Microarchitecture?

The median salary approximately calculated from salary profiles measured so far is ₹32.9lakhs per year.

How is the age distributed among employees who know Microarchitecture?

36% of employees lie between 26-31 yrs . 27% of the employees fall in the age group of 21-26 yrs .

Salary Brackets

Percentage
10-20 lakhs	10-20 lakhs Percentage : 27
20-30 lakhs	20-30 lakhs Percentage : 9
30-40 lakhs	30-40 lakhs Percentage : 36
40-50 lakhs	40-50 lakhs Percentage : 18
> 50 lakhs	> 50 lakhs Percentage : 9

Age Brackets

Percentage
21-26 yrs	21-26 yrs Percentage : 27
26-31 yrs	26-31 yrs Percentage : 36
31-36 yrs	31-36 yrs Percentage : 18

Skills

Trending

microarchitecture

100 %

0 %

universal verification methodology (uvm)

0 %

c++

0 %

rtl design

0 %

application specific integrated circuits (asic)

0 %

assertion based verification

0 %

Schools

Top

Government College of Technology

36 %

Kongu Polytechnic College

36 %

Birla Institute of Technology and Science

9 %

Delhi Technological University (Formerly DCE)

9 %

International Institute of Information Technology Hyderabad (IIITH)

9 %

Mother's Public School

9 %

National Institute of Technology

9 %

Microarchitecture Salaries

Average salary is ₹33.1lakhs.

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What is the average salary of Microarchitecture?

What is the median salary offered who know Microarchitecture?

How is the age distributed among employees who know Microarchitecture?

How much do Microarchitecture employees make?

What is the average salary of Microarchitecture?

What is the median salary offered who know Microarchitecture?

How is the age distributed among employees who know Microarchitecture?

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