Company	Title	Experience	Annual Salary	School	Skills
Qualcomm Chennai	ASIC Design Engineer - WiFi MAC Design (Engineer)	3.7yrs	Base: ₹18.3lakhs Stocks: ₹6.8lakhs Bonus: ₹1.9lakhs CTC:₹27.0lakhs		Networking-Protocol IP (IEEE 802.11 MAC) RTL Microarchitecture Control & Data-Path Design Verilog HDL SystemVerilog Logic Synthesis (Show More) Static Timing Analysis & SDC Constraints Clock Domain Crossing (CDC) & Reset Domain Crossing (RDC) Synopsys Spyglass (CDC/RDC/Lint/DFT) SystemVerilog Testbenches
Intel Corporation Bengaluru	SoC Architect Male	8yrs		The University of Texas at Austin Delhi Technological University (Formerly DCE)	X86 System On A Chip (Soc) Interconnect Manageability System Architecture Ucie (Show More) Pcie Hardware Design Cache Coherency Operating Systems Python Machine Learning Axi Amba Ahb Apb Logic Synthesis Physical Design Dft Rtl Design Cdc Verilog Systemverilog Rdc Lint Arm Cortex-m Arm Architecture Functional Safety Iso 26262 Advanced Driver-assistance Systems (Adas) Requirements Traceability Microarchitecture Vlsi Cmos Vhdl Static Timing Analysis Embedded Systems C Robotics Matlab Image Processing Html 5 Css3 Javascript Html C++
Texas Instruments Bengaluru	Digital Design Engineer (26)	3.8yrs	Base: ₹28.5lakhs Stocks: - Bonus: ₹4.4lakhs CTC:₹32.9lakhs	Government College of Technology Kongu Polytechnic College	Area Optimization Voltus Microarchitecture Tcsh Universal Verification Methodology (Uvm) Test Planning (Show More) Assertion Based Verification Field-programmable Gate Arrays (Fpga) Simvision Tempus Cadence Virtuoso Physical Design Innovus Genus Conformal Jasper Gold Python Xcelium Vim Bash Digital Circuit Design Rtl Design Conformal Lec Computer Hardware Troubleshooting Verilog Hdl Perl Git Linux Centos Windows Computer Hardware C Microsoft Word Microsoft Excel Microsoft Powerpoint Systemverilog Upf Tcl Modelsim Circuit Analysis Computer Hardware Assembly Computer Hardware Installation Rtl Coding Logic Synthesis Cdc Lint Static Timing Analysis Low-power Design Application-specific Integrated Circuits (Asic) Computer Architecture System On A Chip (Soc) Finite State Machines Rtl-to-gdsii Flow Formal Verification
Texas Instruments Bengaluru	Digital Design Engineer	3.7yrs	Base: ₹28.5lakhs Stocks: - Bonus: ₹4.4lakhs CTC:₹32.9lakhs	Government College of Technology Kongu Polytechnic College	Area Optimization Voltus Microarchitecture Tcsh Universal Verification Methodology (Uvm) Test Planning (Show More) Assertion Based Verification Field-programmable Gate Arrays (Fpga) Simvision Tempus Cadence Virtuoso Physical Design Innovus Genus Conformal Jasper Gold Python Xcelium Vim Bash Digital Circuit Design Rtl Design Conformal Lec Computer Hardware Troubleshooting Verilog Hdl Perl Git Linux Centos Windows Computer Hardware C Microsoft Word Microsoft Excel Microsoft Powerpoint Systemverilog Upf Tcl Modelsim Circuit Analysis Computer Hardware Assembly Computer Hardware Installation Rtl Coding Logic Synthesis Cdc Lint Static Timing Analysis Low-power Design Application-specific Integrated Circuits (Asic) Computer Architecture System On A Chip (Soc) Finite State Machines Rtl-to-gdsii Flow Formal Verification
Samsung Electronics Noida	Engineer	2.8yrs	Base: ₹12.4lakhs Stocks: - Bonus: ₹2.1lakhs CTC:₹14.5lakhs	National Institute of Technology	Verilog HDL SystemVerilog Logic Synthesis
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Intel Santa Clara	Staff Engineer Male	16.3yrs		Indian Institute of Technology P.g. College of Law	Functional Verification Formal Verification Eda Systemverilog Perl Low Power Design (Show More) Tcl Soc Logic Synthesis Vlsi Asic Rtl Design Power Management Semiconductors Cadence Debugging Verilog Static Timing Analysis Cad Vhdl Physical Design Embedded Systems Open Verification Methodology Integrated Circuit Design Rtl Coding Amba Ahb Usb Analog Arm Timing Closure Modelsim Primetime Fpga Ncsim Ic Cmos Specman Dft
MediaTek Bengaluru	Senior Engineer Male	16.1yrs	CTC:₹25.0lakhs	Sandeepani School of VLSI Design Govt. Engg. College Bikaner	Static Timing Analysis ASIC Verilog Logic Synthesis Debugging Semiconductors (Show More) FPGA EDA SoC VLSI Functional Verification STA Synthesis ModelSim Perl Primetime TCL VHDL RTL design Physical Design System on a Chip (SoC) Application-Specific Integrated Circuits (ASIC) Conformal LEC Timing Closure Tweaker
AMD Bengaluru	Senior Silicon Design Engineer	7.2yrs	Base: ₹31.0lakhs Stocks: ₹8.6lakhs (Today) (86.0%) ₹16.0L Bonus: ₹3.1lakhs CTC:₹42.7lakhs (Today) (17.3%) ₹50.1L		Logic Synthesis Pnr Clocking Timing Closure Timing Primetime (Show More) Verilog Cadence Innovus Cadence Genus Low-power Design
Mentor Graphics Delhi	Senior Member Consulting Staff Male	9yrs	CTC:₹30.0lakhs	Indian Institute of Technology (IIT)	VHDL Unix TCL CMake C Algorithms (Show More) Data Structures STL Logic Synthesis Perl C++ Verilog
Actel India Hyderabad	Staff Software Engineer Male	10.5yrs	CTC:₹20.0lakhs	Indian Institute of Technology (IIT)	Logic Synthesis EDA C++

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Frequently asked questions

How much do Logic Synthesis employees make?

Employees who know Logic Synthesis earn an average of ₹40.3lakhs, mostly ranging from ₹27.4lakhs per year to ₹105.3lakhs per year based on 10 profiles. The top 10% of employees earn more than ₹69.0lakhs per year.

What is the average salary of Logic Synthesis?

Average salary of an employee who know Logic Synthesis is ₹40.3lakhs.

What is the median salary offered who know Logic Synthesis?

The median salary approximately calculated from salary profiles measured so far is ₹31.5lakhs per year.

How is the age distributed among employees who know Logic Synthesis?

30% of employees lie between 21-26 yrs . 30% of the employees fall in the age group of 31-36 yrs .

Frequently asked questions

How much do Logic Synthesis employees make?

What is the average salary of Logic Synthesis?

Average salary of an employee who know Logic Synthesis is ₹40.3lakhs.

What is the median salary offered who know Logic Synthesis?

The median salary approximately calculated from salary profiles measured so far is ₹31.5lakhs per year.

How is the age distributed among employees who know Logic Synthesis?

30% of employees lie between 21-26 yrs . 30% of the employees fall in the age group of 31-36 yrs .

Salary Brackets

10-20 lakhs10%
20-30 lakhs30%
30-40 lakhs30%
40-50 lakhs10%
> 50 lakhs20%

Age Brackets

21-26 yrs33%
26-31 yrs11%
31-36 yrs33%
36-41 yrs22%

Logic Synthesis Salaries

Average salary is ₹40.3lakhs.

Similar Searches

How much do Logic Synthesis employees make?

What is the average salary of Logic Synthesis?

What is the median salary offered who know Logic Synthesis?

How is the age distributed among employees who know Logic Synthesis?

How much do Logic Synthesis employees make?

What is the average salary of Logic Synthesis?

What is the median salary offered who know Logic Synthesis?

How is the age distributed among employees who know Logic Synthesis?

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