Company	Title	Experience	Annual Salary	School	Skills
Texas Instruments India Bengaluru	Digital Design Engineer (28)	5.8yrs		Government College of Technology Kongu Polytechnic College	Xilinx Vivado Fpga Prototyping Rtl Verification Universal Verification Methodology (Uvm) Assertion Based Verification Field-programmable Gate Arrays (Fpga) (Show More) Microarchitecture Power Analysis Area Optimization Test Planning
Texas Instruments Bengaluru	Digital Design Engineer (26)	5.7yrs		Government College of Technology Kongu Polytechnic College	Xilinx Vivado Fpga Prototyping Rtl Verification Universal Verification Methodology (Uvm) Assertion Based Verification Field-programmable Gate Arrays (Fpga) (Show More) Microarchitecture Power Analysis Area Optimization Test Planning
Arm Bengaluru	Verification Engineer	3.5yrs	Base: ₹26.8lakhs Stocks: - Bonus: - CTC:₹26.8lakhs	Model Engineering College Govt. Boys Higher Secondary School	Universal Verification Methodology (Uvm) Systemverilog Assertion Based Verification Functional Verification Code Coverage Formal Verification (Show More) Verilog-a Digital Electronics System On A Chip (Soc) Very-large-scale Integration (Vlsi)
Qualcomm Bengaluru	Senior Staff Engineer	14.2yrs	Base: ₹71.1lakhs Stocks: ₹49.8lakhs (Today) (7.2%) ₹46.2L Bonus: ₹12.8lakhs CTC:₹133.7lakhs (Today) (2.7%) ₹130.1L	Indian Institute of Technology Savitribai Phule Pune University	Verilog Integrated Circuit Design Vlsi Fpga Uvm Formal Verification (Show More) Assertion Based Verification Soc Circuit Design Processors
Microchip Technology Inc. Chennai	ASIC Verification Engineer	2.4yrs	Base: ₹12.8lakhs Stocks: - Bonus: - CTC:₹12.8lakhs	Model Engineering College Govt. Boys Higher Secondary School	Verilog-a Sv Ethernet Universal Verification Methodology (Uvm) Systemverilog Assertion Based Verification (Show More) Functional Verification Code Coverage Verilog Problem Solving Digital Electronics Formal Verification Linux Perl C C++ System On A Chip (Soc) Very-large-scale Integration (Vlsi) Application-specific Integrated Circuits (Asic) Microsoft Office
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Texas Instruments Bengaluru	Digital Design Engineer	4.6yrs	Base: ₹28.5lakhs Stocks: - Bonus: ₹4.4lakhs CTC:₹32.9lakhs	Government College of Technology Kongu Polytechnic College	Rdc Xilinx Vivado Fpga Prototyping Technical Documentation Technical Drawing Rtl Verification (Show More) Universal Asynchronous Receiver/transmitter (Uart) Spi Power Analysis Area Optimization Voltus Microarchitecture Tcsh Universal Verification Methodology (Uvm) Test Planning Assertion Based Verification Field-programmable Gate Arrays (Fpga) Simvision Tempus Cadence Virtuoso
Microchip Technology Inc. Chennai	Verification Engineer	2.2yrs	Base: ₹11.8lakhs Stocks: - Bonus: - CTC:₹11.8lakhs	Model Engineering College Govt. Boys Higher Secondary School	Universal Verification Methodology (Uvm) Systemverilog Verilog Assertion Based Verification Problem Solving Digital Electronics (Show More) Formal Verification Functional Verification Linux Perl C C++ System On A Chip (Soc) Very-large-scale Integration (Vlsi) Application-specific Integrated Circuits (Asic) Microsoft Office Communication Engineering
Texas Instruments Bengaluru	Digital Design Engineer (26)	3.8yrs	Base: ₹28.5lakhs Stocks: - Bonus: ₹4.4lakhs CTC:₹32.9lakhs	Government College of Technology Kongu Polytechnic College	Area Optimization Voltus Microarchitecture Tcsh Universal Verification Methodology (Uvm) Test Planning (Show More) Assertion Based Verification Field-programmable Gate Arrays (Fpga) Simvision Tempus Cadence Virtuoso Physical Design Innovus Genus Conformal Jasper Gold Python Xcelium Vim Bash Digital Circuit Design Rtl Design Conformal Lec Computer Hardware Troubleshooting Verilog Hdl Perl Git Linux Centos Windows Computer Hardware C Microsoft Word Microsoft Excel Microsoft Powerpoint Systemverilog Upf Tcl Modelsim Circuit Analysis Computer Hardware Assembly Computer Hardware Installation Rtl Coding Logic Synthesis Cdc Lint Static Timing Analysis Low-power Design Application-specific Integrated Circuits (Asic) Computer Architecture System On A Chip (Soc) Finite State Machines Rtl-to-gdsii Flow Formal Verification
Texas Instruments Bengaluru	Digital Design Engineer	3.7yrs	Base: ₹28.5lakhs Stocks: - Bonus: ₹4.4lakhs CTC:₹32.9lakhs	Government College of Technology Kongu Polytechnic College	Area Optimization Voltus Microarchitecture Tcsh Universal Verification Methodology (Uvm) Test Planning (Show More) Assertion Based Verification Field-programmable Gate Arrays (Fpga) Simvision Tempus Cadence Virtuoso Physical Design Innovus Genus Conformal Jasper Gold Python Xcelium Vim Bash Digital Circuit Design Rtl Design Conformal Lec Computer Hardware Troubleshooting Verilog Hdl Perl Git Linux Centos Windows Computer Hardware C Microsoft Word Microsoft Excel Microsoft Powerpoint Systemverilog Upf Tcl Modelsim Circuit Analysis Computer Hardware Assembly Computer Hardware Installation Rtl Coding Logic Synthesis Cdc Lint Static Timing Analysis Low-power Design Application-specific Integrated Circuits (Asic) Computer Architecture System On A Chip (Soc) Finite State Machines Rtl-to-gdsii Flow Formal Verification
Cadence Bengaluru	Lead Verification Engineer	4.8yrs	Base: ₹21.4lakhs Stocks: ₹3.8lakhs (Today) (7.9%) ₹3.5L Bonus: ₹2.6lakhs CTC:₹27.8lakhs (Today) (1.1%) ₹27.5L		Assertion Based Verification Formal Verification Universal Verification Methodology (Uvm) Systemverilog Verilog Design Verification (Show More) Test Planning Problem Solving Microarchitecture Scripting

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Frequently asked questions

How much do Assertion Based Verification employees make?

Employees who know Assertion Based Verification earn an average of ₹40.9lakhs, mostly ranging from ₹32.1lakhs per year to ₹124.6lakhs per year based on 12 profiles. The top 10% of employees earn more than ₹50.4lakhs per year.

What is the average salary of Assertion Based Verification?

Average salary of an employee who know Assertion Based Verification is ₹40.9lakhs.

What is the median salary offered who know Assertion Based Verification?

The median salary approximately calculated from salary profiles measured so far is ₹32.9lakhs per year.

How is the age distributed among employees who know Assertion Based Verification?

42% of employees lie between 21-26 yrs . 25% of the employees fall in the age group of 26-31 yrs .

Frequently asked questions

How much do Assertion Based Verification employees make?

What is the average salary of Assertion Based Verification?

Average salary of an employee who know Assertion Based Verification is ₹40.9lakhs.

What is the median salary offered who know Assertion Based Verification?

The median salary approximately calculated from salary profiles measured so far is ₹32.9lakhs per year.

How is the age distributed among employees who know Assertion Based Verification?

42% of employees lie between 21-26 yrs . 25% of the employees fall in the age group of 26-31 yrs .

Salary Brackets

Percentage
10-20 lakhs	10-20 lakhs Percentage : 17
20-30 lakhs	20-30 lakhs Percentage : 17
30-40 lakhs	30-40 lakhs Percentage : 33
40-50 lakhs	40-50 lakhs Percentage : 17
> 50 lakhs	> 50 lakhs Percentage : 17

Age Brackets

Percentage
21-26 yrs	21-26 yrs Percentage : 42
26-31 yrs	26-31 yrs Percentage : 25
31-36 yrs	31-36 yrs Percentage : 25

Skills

Trending

assertion based verification

100 %

universal verification methodology (uvm)

0 %

formal verification

0 %

linux

0 %

microarchitecture

0 %

perl

0 %

Assertion Based Verification Salaries

Average salary is ₹40.9lakhs.

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How much do Assertion Based Verification employees make?

What is the average salary of Assertion Based Verification?

What is the median salary offered who know Assertion Based Verification?

How is the age distributed among employees who know Assertion Based Verification?

How much do Assertion Based Verification employees make?

What is the average salary of Assertion Based Verification?

What is the median salary offered who know Assertion Based Verification?

How is the age distributed among employees who know Assertion Based Verification?

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