Assertion Based Verification Salaries

5 verified profiles
Last updated on December 21, 2024
Average salary is ₹48.8lakhs.

Employees who know Assertion Based Verification earn an average of ₹48.8lakhs, mostly ranging from ₹32.9lakhs to ₹129.7lakhs based on 5 profiles.

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Salary Profiles
Company
Title
Experience
Annual Salary
School
Skills
2.2yrs

Base: ₹11.8lakhs

Stocks: -

Bonus: -

CTC:₹11.8lakhs

4.1yrs

Base: ₹28.5lakhs

Stocks: -

Bonus: ₹4.4lakhs

CTC:₹32.9lakhs

Power Analysis Area Optimization Voltus Microarchitecture Tcsh Universal Verification Methodology (Uvm) (Show More) Test Planning Assertion Based Verification Field-programmable Gate Arrays (Fpga) Simvision Tempus Cadence Virtuoso Physical Design Innovus Genus Conformal Jasper Gold Python Xcelium Vim Bash Digital Circuit Design Rtl Design Conformal Lec Computer Hardware Troubleshooting Verilog Hdl Perl Git Linux Centos Windows Computer Hardware C Microsoft Word Microsoft Excel Microsoft Powerpoint Systemverilog Upf Tcl Modelsim Circuit Analysis Computer Hardware Assembly Computer Hardware Installation Rtl Coding Logic Synthesis Cdc Lint Static Timing Analysis Low-power Design Application-specific Integrated Circuits (Asic) Computer Architecture System On A Chip (Soc) Finite State Machines Rtl-to-gdsii Flow Formal Verification
Qualcomm
Bengaluru
12.5yrs

Base: ₹71.1lakhs

Stocks: ₹49.8lakhs

Bonus: ₹12.8lakhs

CTC:₹133.7lakhs

3.8yrs

Base: ₹28.5lakhs

Stocks: -

Bonus: ₹4.4lakhs

CTC:₹32.9lakhs

Area Optimization Voltus Microarchitecture Tcsh Universal Verification Methodology (Uvm) Test Planning (Show More) Assertion Based Verification Field-programmable Gate Arrays (Fpga) Simvision Tempus Cadence Virtuoso Physical Design Innovus Genus Conformal Jasper Gold Python Xcelium Vim Bash Digital Circuit Design Rtl Design Conformal Lec Computer Hardware Troubleshooting Verilog Hdl Perl Git Linux Centos Windows Computer Hardware C Microsoft Word Microsoft Excel Microsoft Powerpoint Systemverilog Upf Tcl Modelsim Circuit Analysis Computer Hardware Assembly Computer Hardware Installation Rtl Coding Logic Synthesis Cdc Lint Static Timing Analysis Low-power Design Application-specific Integrated Circuits (Asic) Computer Architecture System On A Chip (Soc) Finite State Machines Rtl-to-gdsii Flow Formal Verification
3.7yrs

Base: ₹28.5lakhs

Stocks: -

Bonus: ₹4.4lakhs

CTC:₹32.9lakhs

Area Optimization Voltus Microarchitecture Tcsh Universal Verification Methodology (Uvm) Test Planning (Show More) Assertion Based Verification Field-programmable Gate Arrays (Fpga) Simvision Tempus Cadence Virtuoso Physical Design Innovus Genus Conformal Jasper Gold Python Xcelium Vim Bash Digital Circuit Design Rtl Design Conformal Lec Computer Hardware Troubleshooting Verilog Hdl Perl Git Linux Centos Windows Computer Hardware C Microsoft Word Microsoft Excel Microsoft Powerpoint Systemverilog Upf Tcl Modelsim Circuit Analysis Computer Hardware Assembly Computer Hardware Installation Rtl Coding Logic Synthesis Cdc Lint Static Timing Analysis Low-power Design Application-specific Integrated Circuits (Asic) Computer Architecture System On A Chip (Soc) Finite State Machines Rtl-to-gdsii Flow Formal Verification

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Frequently asked questions
How much do Assertion Based Verification employees make?

Employees who know Assertion Based Verification earn an average of ₹48.8lakhs, mostly ranging from ₹32.9lakhs per year to ₹129.7lakhs per year based on 5 profiles. The top 10% of employees earn more than ₹89.3lakhs per year.

What is the average salary of Assertion Based Verification?

Average salary of an employee who know Assertion Based Verification is ₹48.8lakhs.

What is the median salary offered who know Assertion Based Verification?

The median salary approximately calculated from salary profiles measured so far is ₹32.9lakhs per year.

How is the age distributed among employees who know Assertion Based Verification?

This group has a predominantly younger workforce. 80% of employees lie between 21-26 yrs . 20% of the employees fall in the age group of 31-36 yrs .

Frequently asked questions
How much do Assertion Based Verification employees make?

Employees who know Assertion Based Verification earn an average of ₹48.8lakhs, mostly ranging from ₹32.9lakhs per year to ₹129.7lakhs per year based on 5 profiles. The top 10% of employees earn more than ₹89.3lakhs per year.

What is the average salary of Assertion Based Verification?

Average salary of an employee who know Assertion Based Verification is ₹48.8lakhs.

What is the median salary offered who know Assertion Based Verification?

The median salary approximately calculated from salary profiles measured so far is ₹32.9lakhs per year.

How is the age distributed among employees who know Assertion Based Verification?

This group has a predominantly younger workforce. 80% of employees lie between 21-26 yrs . 20% of the employees fall in the age group of 31-36 yrs .

Salary Brackets
Percentage
10-20 lakhs 10-20 lakhs
Percentage : 20
30-40 lakhs 30-40 lakhs
Percentage : 60
> 50 lakhs > 50 lakhs
Percentage : 20
Age Brackets
Percentage
21-26 yrs 21-26 yrs
Percentage : 80
31-36 yrs 31-36 yrs
Percentage : 20
Skills
Trending
assertion based verification
100 %
c
0 %
formal verification
0 %
application specific integrated circuits (asic)
0 %
linux
0 %
perl
0 %
system on a chip (soc)
0 %
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