VMware Mts Asic Layout Design Engineer Palo Alto Salaries
180 verified profilesAverage Annual Total Compensation is $210k
Employees at VMware as Mts Asic Layout Design Engineer in Palo Alto earn an average of $210k, mostly ranging from $189k to $324k based on 180 profiles.
| 👨💻 Male | $211k Male Average Salary : $ 211 k |
|---|---|
| 👩💻 Female | $195k Female Average Salary : $ 195 k |
Backend Engineer
(MTS 3) Female | Base: $153k Stocks: $59k Bonus: $23k TC:$234k | 7yrs | NA | Masters | Works in Palo Alto, CA | ||
Backend Engineer
(MTS 3) Female | Base: $155k Stocks: $15k Bonus: $32k TC:$202k | 4yrs | NA | Masters | Works in Palo Alto, CA | ||
Data Engineer
(Senior MTS) Male | Base: $206k Stocks: $44k Bonus: $39k TC:$289k | 8yrs | NA | Masters | Works in Palo Alto, CA | ||
DevOps Engineer
(MTS 3) Female | Base: $176k Stocks: $2k Bonus: - TC:$178k | 6yrs | NA | Masters | Works in Palo Alto, CA | ||
Backend Engineer
(MTS 3) Female | Base: $164k Stocks: $49k Bonus: - TC:$213k | 6yrs | NA | Masters | Works in Palo Alto, CA | ||
Backend Engineer
(MTS 2) Male | Base: $151k Stocks: $49k Bonus: $19k TC:$219k | 2yrs | NA | Masters | Works in Palo Alto, CA | ||
Networking Engineer
(Senior MTS) Male | Base: $194k Stocks: $39k Bonus: $34k TC:$267k | 8yrs | NA | Masters | Works in Palo Alto, CA | ||
Backend Engineer
(Senior MTS) Male | Base: $178k Stocks: $25k Bonus: $30k TC:$233k | 6yrs | NA | Masters | Works in Palo Alto, CA | ||
Networking Engineer
(MTS 2) Male | Base: $152k Stocks: $40k Bonus: $22k TC:$214k | 2yrs | NA | Masters | Works in Palo Alto, CA | ||
Networking Engineer
(P3) Female | Base: $162k Stocks: $59k Bonus: $5k TC:$225k | 12yrs | NA | Masters | Works in Palo Alto, CA |
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VMware Mts Asic Layout Design Engineer Palo Alto salary levels ranges from MTS 1 (Software Engineer) upto Senior MTS (Software Engineer), with Senior MTS (Software Engineer) level earning average salary of $273k along with $49k worth of stock options.
How much do VMware Mts Asic Layout Design Engineer Palo Alto employees make?
Employees at VMware as Mts Asic Layout Design Engineer in Palo Alto earn an average of $210k, mostly ranging from $189k per year to $324k per year based on 180 profiles. The top 10% of employees earn more than $267k per year.
What is the average salary of VMware Mts Asic Layout Design Engineer Palo Alto?
Average salary of an employee at VMware as Mts Asic Layout Design Engineer in Palo Alto is $210k.
What is the highest salary offered at VMware as Mts Asic Layout Design Engineer in Palo Alto?
Highest reported salary offered at VMware as Mts Asic Layout Design Engineer in Palo Alto is $335k. The top 10% of employees earn more than $267k per year. The top 1% earn more than a whopping $324k per year.
What are the most common skills required at VMware as Mts Asic Layout Design Engineer in Palo Alto?
What are the highest paying jobs at VMware as Mts Asic Layout Design Engineer in Palo Alto?
The top 5 highest paying jobs at VMware as Mts Asic Layout Design Engineer in Palo Alto with reported salaries are:
software engineer - $210k per year
What are the new grad salaries at VMware as Mts Asic Layout Design Engineer in Palo Alto?
software engineer - $165k per year
What is the median salary offered at VMware as Mts Asic Layout Design Engineer in Palo Alto?
The median salary approximately calculated from salary profiles measured so far is $206k per year.
How is the age distributed among employees at VMware as Mts Asic Layout Design Engineer in Palo Alto?
What qualifications do employees have at VMware as Mts Asic Layout Design Engineer in Palo Alto?
Which schools do employees working at VMware as Mts Asic Layout Design Engineer in Palo Alto went to?
How much do VMware Mts Asic Layout Design Engineer Palo Alto employees make?
Employees at VMware as Mts Asic Layout Design Engineer in Palo Alto earn an average of $210k, mostly ranging from $189k per year to $324k per year based on 180 profiles. The top 10% of employees earn more than $267k per year.
What is the average salary of VMware Mts Asic Layout Design Engineer Palo Alto?
Average salary of an employee at VMware as Mts Asic Layout Design Engineer in Palo Alto is $210k.
What is the highest salary offered at VMware as Mts Asic Layout Design Engineer in Palo Alto?
Highest reported salary offered at VMware as Mts Asic Layout Design Engineer in Palo Alto is $335k. The top 10% of employees earn more than $267k per year. The top 1% earn more than a whopping $324k per year.
What are the most common skills required at VMware as Mts Asic Layout Design Engineer in Palo Alto?
What are the highest paying jobs at VMware as Mts Asic Layout Design Engineer in Palo Alto?
The top 5 highest paying jobs at VMware as Mts Asic Layout Design Engineer in Palo Alto with reported salaries are:
software engineer - $210k per year
What are the new grad salaries at VMware as Mts Asic Layout Design Engineer in Palo Alto?
software engineer - $165k per year
What is the median salary offered at VMware as Mts Asic Layout Design Engineer in Palo Alto?
The median salary approximately calculated from salary profiles measured so far is $206k per year.
How is the age distributed among employees at VMware as Mts Asic Layout Design Engineer in Palo Alto?
What qualifications do employees have at VMware as Mts Asic Layout Design Engineer in Palo Alto?
Which schools do employees working at VMware as Mts Asic Layout Design Engineer in Palo Alto went to?
| 100-200 k | 100-200 k Percentage : 44 |
|---|---|
| 200-300 k | 200-300 k Percentage : 52 |
| 300-400 k | 300-400 k Percentage : 4 |
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