Company	Title	Experience	Annual Salary	School	Skills
Texas Instruments Bengaluru	Digital Design Engineer (26)	3.8yrs	Base: ₹28.5lakhs Stocks: - Bonus: ₹4.4lakhs CTC:₹32.9lakhs	Government College of Technology Kongu Polytechnic College	Area Optimization Voltus Microarchitecture Tcsh Universal Verification Methodology (Uvm) Test Planning (Show More) Assertion Based Verification Field-programmable Gate Arrays (Fpga) Simvision Tempus Cadence Virtuoso Physical Design Innovus Genus Conformal Jasper Gold Python Xcelium Vim Bash Digital Circuit Design Rtl Design Conformal Lec Computer Hardware Troubleshooting Verilog Hdl Perl Git Linux Centos Windows Computer Hardware C Microsoft Word Microsoft Excel Microsoft Powerpoint Systemverilog Upf Tcl Modelsim Circuit Analysis Computer Hardware Assembly Computer Hardware Installation Rtl Coding Logic Synthesis Cdc Lint Static Timing Analysis Low-power Design Application-specific Integrated Circuits (Asic) Computer Architecture System On A Chip (Soc) Finite State Machines Rtl-to-gdsii Flow Formal Verification
Texas Instruments Bengaluru	Digital Design Engineer	3.7yrs	Base: ₹28.5lakhs Stocks: - Bonus: ₹4.4lakhs CTC:₹32.9lakhs	Government College of Technology Kongu Polytechnic College	Area Optimization Voltus Microarchitecture Tcsh Universal Verification Methodology (Uvm) Test Planning (Show More) Assertion Based Verification Field-programmable Gate Arrays (Fpga) Simvision Tempus Cadence Virtuoso Physical Design Innovus Genus Conformal Jasper Gold Python Xcelium Vim Bash Digital Circuit Design Rtl Design Conformal Lec Computer Hardware Troubleshooting Verilog Hdl Perl Git Linux Centos Windows Computer Hardware C Microsoft Word Microsoft Excel Microsoft Powerpoint Systemverilog Upf Tcl Modelsim Circuit Analysis Computer Hardware Assembly Computer Hardware Installation Rtl Coding Logic Synthesis Cdc Lint Static Timing Analysis Low-power Design Application-specific Integrated Circuits (Asic) Computer Architecture System On A Chip (Soc) Finite State Machines Rtl-to-gdsii Flow Formal Verification
Samsung Electronics Noida	Engineer	2.8yrs	Base: ₹12.4lakhs Stocks: - Bonus: ₹2.1lakhs CTC:₹14.5lakhs	National Institute of Technology	Verilog HDL SystemVerilog Logic Synthesis
Samsung Electronics Bangalore	Senior Engineer - SoC Verification Male	2yrs	Base: ₹17.5lakhs Stocks: - Bonus: ₹0.5lakhs CTC:₹18.0lakhs	Jadavpur University	RTL Coding C Python UVM System Verilog Verilog HDL (Show More) C++11
Magna Steyr India Pune	Associate Engineer Female	5.3yrs	CTC:₹30.0lakhs	La Trobe University Pune University	Embedded Software Development Simulation Electronics Automation Design Digital Signal Processing Embedded C Automation Testing (Show More) Verilog HDL C C++ Matlab SCILAB Lab view CANaylzer CANoe VSPY Test Complete Manual Testing Vehicle Testing Hil Testing C C++ Embedded C JAVA SCRIPT MS Visual Studio MS OFFICE CANaylzer CANoe VSPY
Xilinx India Technologies Hyderabad	Design Engineer 2	3yrs	CTC:₹16.0lakhs	School of Information Science Dr. SMCE	Design Engineer 2 Team Lead/Tech Lead IT Project Management Design Engineering VLSI Design Quality Assurance (Show More) System Verilog Debugging Client Servicing Design Analysis Solution Architecture Bug Tracking Application Support JIRA Verilog HDL

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Frequently asked questions

How much do Verilog Hdl employees make?

Employees who know Verilog Hdl earn an average of ₹24.1lakhs, mostly ranging from ₹17.5lakhs per year to ₹32.9lakhs per year based on 6 profiles. The top 10% of employees earn more than ₹32.9lakhs per year.

What is the average salary of Verilog Hdl?

Average salary of an employee who know Verilog Hdl is ₹24.1lakhs.

What is the median salary offered who know Verilog Hdl?

The median salary approximately calculated from salary profiles measured so far is ₹24.0lakhs per year.

How is the age distributed among employees who know Verilog Hdl?

This group has a predominantly younger workforce. 67% of employees lie between 21-26 yrs . 33% of the employees fall in the age group of 26-31 yrs .

Frequently asked questions

How much do Verilog Hdl employees make?

What is the average salary of Verilog Hdl?

Average salary of an employee who know Verilog Hdl is ₹24.1lakhs.

What is the median salary offered who know Verilog Hdl?

The median salary approximately calculated from salary profiles measured so far is ₹24.0lakhs per year.

How is the age distributed among employees who know Verilog Hdl?

This group has a predominantly younger workforce. 67% of employees lie between 21-26 yrs . 33% of the employees fall in the age group of 26-31 yrs .

Salary Brackets

Percentage
10-20 lakhs	10-20 lakhs Percentage : 50
30-40 lakhs	30-40 lakhs Percentage : 50

Age Brackets

Percentage
21-26 yrs	21-26 yrs Percentage : 67
26-31 yrs	26-31 yrs Percentage : 33

Skills

Trending

verilog hdl

100 %

0 %

logic synthesis

0 %

python

0 %

rtl coding

0 %

systemverilog

0 %

application specific integrated circuits (asic)

0 %

Schools

Top

Government College of Technology

33 %

Kongu Polytechnic College

33 %

Dr. SMCE

17 %

Jadavpur University

17 %

La Trobe University

17 %

National Institute of Technology

17 %

Pune University

17 %

Verilog Hdl Salaries

Average salary is ₹24.1lakhs.

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How much do Verilog Hdl employees make?

What is the average salary of Verilog Hdl?

What is the median salary offered who know Verilog Hdl?

How is the age distributed among employees who know Verilog Hdl?

How much do Verilog Hdl employees make?

What is the average salary of Verilog Hdl?

What is the median salary offered who know Verilog Hdl?

How is the age distributed among employees who know Verilog Hdl?

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