Verilog Hdl Salaries

7 verified profiles
Last updated on December 24, 2024
Average salary is ₹25.3lakhs.

Employees who know Verilog Hdl earn an average of ₹25.3lakhs, mostly ranging from ₹19.2lakhs to ₹32.9lakhs based on 7 profiles.

👩‍💻 Female ₹30lakhs Female
Average Salary : ₹ 30 lakhs
👨‍💻 Male ₹18lakhs Male
Average Salary : ₹ 18 lakhs
For every ₹100 paid to men, women are paid ₹167
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Salary Profiles
Company
Title
Experience
Annual Salary
School
Skills
4.1yrs

Base: ₹28.5lakhs

Stocks: -

Bonus: ₹4.4lakhs

CTC:₹32.9lakhs

Power Analysis Area Optimization Voltus Microarchitecture Tcsh Universal Verification Methodology (Uvm) (Show More) Test Planning Assertion Based Verification Field-programmable Gate Arrays (Fpga) Simvision Tempus Cadence Virtuoso Physical Design Innovus Genus Conformal Jasper Gold Python Xcelium Vim Bash Digital Circuit Design Rtl Design Conformal Lec Computer Hardware Troubleshooting Verilog Hdl Perl Git Linux Centos Windows Computer Hardware C Microsoft Word Microsoft Excel Microsoft Powerpoint Systemverilog Upf Tcl Modelsim Circuit Analysis Computer Hardware Assembly Computer Hardware Installation Rtl Coding Logic Synthesis Cdc Lint Static Timing Analysis Low-power Design Application-specific Integrated Circuits (Asic) Computer Architecture System On A Chip (Soc) Finite State Machines Rtl-to-gdsii Flow Formal Verification
3.8yrs

Base: ₹28.5lakhs

Stocks: -

Bonus: ₹4.4lakhs

CTC:₹32.9lakhs

Area Optimization Voltus Microarchitecture Tcsh Universal Verification Methodology (Uvm) Test Planning (Show More) Assertion Based Verification Field-programmable Gate Arrays (Fpga) Simvision Tempus Cadence Virtuoso Physical Design Innovus Genus Conformal Jasper Gold Python Xcelium Vim Bash Digital Circuit Design Rtl Design Conformal Lec Computer Hardware Troubleshooting Verilog Hdl Perl Git Linux Centos Windows Computer Hardware C Microsoft Word Microsoft Excel Microsoft Powerpoint Systemverilog Upf Tcl Modelsim Circuit Analysis Computer Hardware Assembly Computer Hardware Installation Rtl Coding Logic Synthesis Cdc Lint Static Timing Analysis Low-power Design Application-specific Integrated Circuits (Asic) Computer Architecture System On A Chip (Soc) Finite State Machines Rtl-to-gdsii Flow Formal Verification
3.7yrs

Base: ₹28.5lakhs

Stocks: -

Bonus: ₹4.4lakhs

CTC:₹32.9lakhs

Area Optimization Voltus Microarchitecture Tcsh Universal Verification Methodology (Uvm) Test Planning (Show More) Assertion Based Verification Field-programmable Gate Arrays (Fpga) Simvision Tempus Cadence Virtuoso Physical Design Innovus Genus Conformal Jasper Gold Python Xcelium Vim Bash Digital Circuit Design Rtl Design Conformal Lec Computer Hardware Troubleshooting Verilog Hdl Perl Git Linux Centos Windows Computer Hardware C Microsoft Word Microsoft Excel Microsoft Powerpoint Systemverilog Upf Tcl Modelsim Circuit Analysis Computer Hardware Assembly Computer Hardware Installation Rtl Coding Logic Synthesis Cdc Lint Static Timing Analysis Low-power Design Application-specific Integrated Circuits (Asic) Computer Architecture System On A Chip (Soc) Finite State Machines Rtl-to-gdsii Flow Formal Verification
2.8yrs

Base: ₹12.4lakhs

Stocks: -

Bonus: ₹2.1lakhs

CTC:₹14.5lakhs

2yrs

Base: ₹17.5lakhs

Stocks: -

Bonus: ₹0.5lakhs

CTC:₹18.0lakhs

5.3yrs

CTC:₹30.0lakhs

3yrs

CTC:₹16.0lakhs

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Frequently asked questions
How much do Verilog Hdl employees make?

Employees who know Verilog Hdl earn an average of ₹25.3lakhs, mostly ranging from ₹19.2lakhs per year to ₹32.9lakhs per year based on 7 profiles. The top 10% of employees earn more than ₹32.9lakhs per year.

What is the average salary of Verilog Hdl?

Average salary of an employee who know Verilog Hdl is ₹25.3lakhs.

What is the median salary offered who know Verilog Hdl?

The median salary approximately calculated from salary profiles measured so far is ₹30.0lakhs per year.

How is the age distributed among employees who know Verilog Hdl?

This group has a predominantly younger workforce. 71% of employees lie between 21-26 yrs . 29% of the employees fall in the age group of 26-31 yrs .

Frequently asked questions
How much do Verilog Hdl employees make?

Employees who know Verilog Hdl earn an average of ₹25.3lakhs, mostly ranging from ₹19.2lakhs per year to ₹32.9lakhs per year based on 7 profiles. The top 10% of employees earn more than ₹32.9lakhs per year.

What is the average salary of Verilog Hdl?

Average salary of an employee who know Verilog Hdl is ₹25.3lakhs.

What is the median salary offered who know Verilog Hdl?

The median salary approximately calculated from salary profiles measured so far is ₹30.0lakhs per year.

How is the age distributed among employees who know Verilog Hdl?

This group has a predominantly younger workforce. 71% of employees lie between 21-26 yrs . 29% of the employees fall in the age group of 26-31 yrs .

Salary Brackets
Percentage
10-20 lakhs 10-20 lakhs
Percentage : 43
30-40 lakhs 30-40 lakhs
Percentage : 57
Age Brackets
Percentage
21-26 yrs 21-26 yrs
Percentage : 71
26-31 yrs 26-31 yrs
Percentage : 29
Skills
Trending
verilog hdl
100 %
c
0 %
logic synthesis
0 %
python
0 %
rtl coding
0 %
systemverilog
0 %
application specific integrated circuits (asic)
0 %
Schools
Top
Government College of Technology
43 %
Kongu Polytechnic College
43 %
Dr. SMCE
14 %
Jadavpur University
14 %
La Trobe University
14 %
National Institute of Technology
14 %
Pune University
14 %
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