Company	Title	Experience	Annual Salary	School	Skills
Google Bengaluru	Design Verification Engineer	8yrs	Base: ₹27.2lakhs Stocks: ₹9.7lakhs Bonus: - CTC:₹36.9lakhs	Birla Institute of Technology	System On A Chip (Soc) Systemverilog Universal Verification Methodology (Uvm) Very-large-scale Integration (Vlsi) Engineering C (Show More) Microsoft Excel Oop Verilog Electronics C++ Linux Rtl Design
Texas Instruments Bengaluru	Digital Design Engineer	4.1yrs	Base: ₹28.5lakhs Stocks: - Bonus: ₹4.4lakhs CTC:₹32.9lakhs	Government College of Technology Kongu Polytechnic College	Power Analysis Area Optimization Voltus Microarchitecture Tcsh Universal Verification Methodology (Uvm) (Show More) Test Planning Assertion Based Verification Field-programmable Gate Arrays (Fpga) Simvision Tempus Cadence Virtuoso Physical Design Innovus Genus Conformal Jasper Gold Python Xcelium Vim Bash Digital Circuit Design Rtl Design Conformal Lec Computer Hardware Troubleshooting Verilog Hdl Perl Git Linux Centos Windows Computer Hardware C Microsoft Word Microsoft Excel Microsoft Powerpoint Systemverilog Upf Tcl Modelsim Circuit Analysis Computer Hardware Assembly Computer Hardware Installation Rtl Coding Logic Synthesis Cdc Lint Static Timing Analysis Low-power Design Application-specific Integrated Circuits (Asic) Computer Architecture System On A Chip (Soc) Finite State Machines Rtl-to-gdsii Flow Formal Verification
Intel Corporation Bengaluru	SoC Architect Male	8yrs		The University of Texas at Austin Delhi Technological University (Formerly DCE)	X86 System On A Chip (Soc) Interconnect Manageability System Architecture Ucie (Show More) Pcie Hardware Design Cache Coherency Operating Systems Python Machine Learning Axi Amba Ahb Apb Logic Synthesis Physical Design Dft Rtl Design Cdc Verilog Systemverilog Rdc Lint Arm Cortex-m Arm Architecture Functional Safety Iso 26262 Advanced Driver-assistance Systems (Adas) Requirements Traceability Microarchitecture Vlsi Cmos Vhdl Static Timing Analysis Embedded Systems C Robotics Matlab Image Processing Html 5 Css3 Javascript Html C++
Mentor Graphics Bengaluru	Lead Engineer	18.6yrs		Indian Institute of Technology Devi Ahilya Vishwavidyalaya	TCL EDA Debugging FPGA RTL design VHDL (Show More) VLSI Verilog ASIC SystemVerilog Xilinx calibre MPC
Texas Instruments Bengaluru	Digital Design Engineer (26)	3.8yrs	Base: ₹28.5lakhs Stocks: - Bonus: ₹4.4lakhs CTC:₹32.9lakhs	Government College of Technology Kongu Polytechnic College	Area Optimization Voltus Microarchitecture Tcsh Universal Verification Methodology (Uvm) Test Planning (Show More) Assertion Based Verification Field-programmable Gate Arrays (Fpga) Simvision Tempus Cadence Virtuoso Physical Design Innovus Genus Conformal Jasper Gold Python Xcelium Vim Bash Digital Circuit Design Rtl Design Conformal Lec Computer Hardware Troubleshooting Verilog Hdl Perl Git Linux Centos Windows Computer Hardware C Microsoft Word Microsoft Excel Microsoft Powerpoint Systemverilog Upf Tcl Modelsim Circuit Analysis Computer Hardware Assembly Computer Hardware Installation Rtl Coding Logic Synthesis Cdc Lint Static Timing Analysis Low-power Design Application-specific Integrated Circuits (Asic) Computer Architecture System On A Chip (Soc) Finite State Machines Rtl-to-gdsii Flow Formal Verification
Texas Instruments Bengaluru	Digital Design Engineer	3.7yrs	Base: ₹28.5lakhs Stocks: - Bonus: ₹4.4lakhs CTC:₹32.9lakhs	Government College of Technology Kongu Polytechnic College	Area Optimization Voltus Microarchitecture Tcsh Universal Verification Methodology (Uvm) Test Planning (Show More) Assertion Based Verification Field-programmable Gate Arrays (Fpga) Simvision Tempus Cadence Virtuoso Physical Design Innovus Genus Conformal Jasper Gold Python Xcelium Vim Bash Digital Circuit Design Rtl Design Conformal Lec Computer Hardware Troubleshooting Verilog Hdl Perl Git Linux Centos Windows Computer Hardware C Microsoft Word Microsoft Excel Microsoft Powerpoint Systemverilog Upf Tcl Modelsim Circuit Analysis Computer Hardware Assembly Computer Hardware Installation Rtl Coding Logic Synthesis Cdc Lint Static Timing Analysis Low-power Design Application-specific Integrated Circuits (Asic) Computer Architecture System On A Chip (Soc) Finite State Machines Rtl-to-gdsii Flow Formal Verification
Cerium Systems Bengaluru	Senior Engineer - RTL Design Male	6.1yrs	Base: ₹15.3lakhs Stocks: - Bonus: - CTC:₹15.3lakhs	Jalpaiguri Government Engineering College	Unix C Perl Verilog Rtl Design And Verifiaction C++ Microsoft Office (Show More) Microsoft Excel Microsoft Word Microsoft Powerpoint Tcl-tk System Verilog For Verification Static Timing Analysis Verilog Tk Systemverilog Genus Hal Python Artificial Intelligence (Ai) C
Maven Silicon Bengaluru	RTL Design - Verification Trainee Male	1.1yrs	Base: ₹11.8lakhs Stocks: - Bonus: ₹0.9lakhs CTC:₹12.7lakhs	Model Engineering College Govt. Boys Higher Secondary School	Verilog Systemverilog Uvm Assertions Verification Asic (Show More)
Samsung semiconductor India R&D Center Bengaluru	Staff Engineer	7.2yrs		Indian Institute Of Information Technology Maven silicon(earlier know as Accel IT Academy)	Algorithms Application Specific Integrated Circuits Asic C C++ Cadence Virtuoso (Show More) Digital Electronics Eda Electronics Field Programmable Gate Arrays Fpga Functional Verification Ic Integrated Circuit Design Linux Matlab Microcontrollers Microprocessors Microsoft Office Modelsim Perl Programming Psl Rtl Coding Rtl Design Semiconductors Shell Scripting Simulations Soc Sourcing Static Timing Analysis System Verilog Systemverilog Testing Verilog Very Large Scale Integration Vhdl Vlsi Xilinx
AMD Bangalore	Senior Member Of Technical Staff Male	18.5yrs		Birla Institute of Technology and Science Indian Institute of Technology	Application Specific Integrated Circuits Asic Debugging Digital Signal Processors Eda Embedded Systems (Show More) Ic Integrated Circuits Low Power Design Modelsim Perl Rtl Design Semiconductors Soc System On A Chip Systemverilog Tcl Testing Verilog Very Large Scale Integration Vlsi

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Frequently asked questions

How much do Systemverilog Bengaluru employees make?

Employees who know Systemverilog in Bengaluru earn an average of ₹47.6lakhs, mostly ranging from ₹32.9lakhs per year to ₹106.8lakhs per year based on 14 profiles. The top 10% of employees earn more than ₹75.6lakhs per year.

What is the average salary of Systemverilog Bengaluru?

Average salary of an employee who know Systemverilog in Bengaluru is ₹47.6lakhs.

What is the median salary offered who know Systemverilog in Bengaluru?

The median salary approximately calculated from salary profiles measured so far is ₹42.5lakhs per year.

How is the age distributed among employees who know Systemverilog in Bengaluru?

29% of employees lie between 21-26 yrs . 29% of the employees fall in the age group of 26-31 yrs .

Frequently asked questions

How much do Systemverilog Bengaluru employees make?

What is the average salary of Systemverilog Bengaluru?

Average salary of an employee who know Systemverilog in Bengaluru is ₹47.6lakhs.

What is the median salary offered who know Systemverilog in Bengaluru?

The median salary approximately calculated from salary profiles measured so far is ₹42.5lakhs per year.

How is the age distributed among employees who know Systemverilog in Bengaluru?

29% of employees lie between 21-26 yrs . 29% of the employees fall in the age group of 26-31 yrs .

Salary Brackets

Percentage
10-20 lakhs	10-20 lakhs Percentage : 14
20-30 lakhs	20-30 lakhs Percentage : 7
30-40 lakhs	30-40 lakhs Percentage : 29
40-50 lakhs	40-50 lakhs Percentage : 14
> 50 lakhs	> 50 lakhs Percentage : 36

Age Brackets

Percentage
21-26 yrs	21-26 yrs Percentage : 29
26-31 yrs	26-31 yrs Percentage : 29
31-36 yrs	31-36 yrs Percentage : 14
> 41 yrs	> 41 yrs Percentage : 21

Skills

Trending

systemverilog

100 %

verilog

0 %

perl

0 %

rtl design

0 %

linux

0 %

modelsim

0 %

Schools

Top

Government College of Technology

21 %

Indian Institute of Technology

21 %

Kongu Polytechnic College

21 %

Birla Institute of Technology

7 %

Birla Institute of Technology and Science

7 %

Delhi Technological University (Formerly DCE)

7 %

Devi Ahilya Vishwavidyalaya

7 %

Systemverilog Bengaluru Salaries

Average salary is ₹47.6lakhs.

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How much do Systemverilog Bengaluru employees make?

What is the average salary of Systemverilog Bengaluru?

What is the median salary offered who know Systemverilog in Bengaluru?

How is the age distributed among employees who know Systemverilog in Bengaluru?

How much do Systemverilog Bengaluru employees make?

What is the average salary of Systemverilog Bengaluru?

What is the median salary offered who know Systemverilog in Bengaluru?

How is the age distributed among employees who know Systemverilog in Bengaluru?

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