Silicon Design Engineer II Salaries

3 verified profiles
Last updated on October 15, 2024
Average salary is ₹19.8lakhs.

Employees as Silicon Design Engineer II earn an average of ₹19.8lakhs, mostly ranging from ₹19.5lakhs to ₹22.6lakhs based on 3 profiles.

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Frequently asked questions
How much do Silicon Design Engineer II employees make?

Employees as Silicon Design Engineer II earn an average of ₹19.8lakhs, mostly ranging from ₹19.5lakhs per year to ₹22.6lakhs per year based on 3 profiles. The top 10% of employees earn more than ₹22.3lakhs per year.

What is the average salary of Silicon Design Engineer II?

Average salary of an employee as Silicon Design Engineer II is ₹19.8lakhs.

What is the median salary offered as Silicon Design Engineer II?

The median salary approximately calculated from salary profiles measured so far is ₹21.1lakhs per year.

How is the age distributed among employees as Silicon Design Engineer II?

This group has a predominantly younger workforce. 67% of employees lie between 21-26 yrs .

Frequently asked questions
How much do Silicon Design Engineer II employees make?

Employees as Silicon Design Engineer II earn an average of ₹19.8lakhs, mostly ranging from ₹19.5lakhs per year to ₹22.6lakhs per year based on 3 profiles. The top 10% of employees earn more than ₹22.3lakhs per year.

What is the average salary of Silicon Design Engineer II?

Average salary of an employee as Silicon Design Engineer II is ₹19.8lakhs.

What is the median salary offered as Silicon Design Engineer II?

The median salary approximately calculated from salary profiles measured so far is ₹21.1lakhs per year.

How is the age distributed among employees as Silicon Design Engineer II?

This group has a predominantly younger workforce. 67% of employees lie between 21-26 yrs .

Salary Brackets
Percentage
10-20 lakhs 10-20 lakhs
Percentage : 33
20-30 lakhs 20-30 lakhs
Percentage : 67
Age Brackets
Percentage
21-26 yrs 21-26 yrs
Percentage : 67
Skills
Trending
c++
67 %
static timing analysis
33 %
system verilog
0 %
verilog
0 %
axi
0 %
c
0 %
cdc
0 %
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