Company	Title	Experience	Annual Salary	School	Skills
Cadence Design Systems India	Lead Solution Engineer	8.9yrs		Nirma University	Schematic Capture Cad Tools Skill Script Pcell Development Test Planning Drc (Show More) Lvs Physical Design Test Cases Cadence Virtuoso Pex Drm Process Design Linux Verilog Sim C C++ Vhdl Perl Research Soc Low-power Design Mixed Signal Analog Circuit Design Testing System On A Chip (Soc) Physical Verification Ic Fabrication Vlsi Cad Pcell Analog Simulation Mixed Signal Simulation Integrated Circuits (Ic) Very-large-scale Integration (Vlsi) Application-specific Integrated Circuits (Asic) Simulations Design Rule Checking (Drc) Layout Versus Schematic (Lvs) Cadence Debugging Eda Floorplanning Electronics Cmos Video Blogging Git Github Goal Setting Priority Management
Texas Instruments Bengaluru	Digital Design Engineer	4.1yrs	Base: ₹28.5lakhs Stocks: - Bonus: ₹4.4lakhs CTC:₹32.9lakhs	Government College of Technology Kongu Polytechnic College	Power Analysis Area Optimization Voltus Microarchitecture Tcsh Universal Verification Methodology (Uvm) (Show More) Test Planning Assertion Based Verification Field-programmable Gate Arrays (Fpga) Simvision Tempus Cadence Virtuoso Physical Design Innovus Genus Conformal Jasper Gold Python Xcelium Vim Bash Digital Circuit Design Rtl Design Conformal Lec Computer Hardware Troubleshooting Verilog Hdl Perl Git Linux Centos Windows Computer Hardware C Microsoft Word Microsoft Excel Microsoft Powerpoint Systemverilog Upf Tcl Modelsim Circuit Analysis Computer Hardware Assembly Computer Hardware Installation Rtl Coding Logic Synthesis Cdc Lint Static Timing Analysis Low-power Design Application-specific Integrated Circuits (Asic) Computer Architecture System On A Chip (Soc) Finite State Machines Rtl-to-gdsii Flow Formal Verification
Qualcomm Bengaluru	Senior Power - Performance Analysis Engineer	3yrs	Base: ₹22.2lakhs Stocks: ₹10.6lakhs (Today) (24.5%) ₹8.0L Bonus: ₹2.9lakhs CTC:₹35.7lakhs (Today) (7.3%) ₹33.1L	Indian Institute of Technology (Banaras Hindu University)	Power And Perf Analysis Performance Validation Qualcomm Soc Architecture Qualcomm Smmu And Ddr Architecture Video Codecs Qualcomm Spectra Isp (Show More) Performance Verification Performance Testing Video Codec Systems Analysis System Performance Performance Analysis Model And Analyze Video Algorithms/features Using A C++ Based Cycle-accurate Video Performance Model Computer Architecture Knowledge Camera/video Subsystem Performance Analysis For Qualcomm Socs Camera/video Performance For Qualcomm Snapdragon Socs Modeling Of Video Codecs For Performance Evaluation Systemc, C/c++, Python C Digital Ic Design Field-programmable Gate Arrays (Fpga) Digital System Design Application-specific Integrated Circuits (Asic) Microcontrollers Electronics Verilog Cmos Digital Integrated Circuit Tcl Ic Technology Tcl-tk Computer Architecture Low-power Design
Texas Instruments Bengaluru	Digital Design Engineer (26)	3.8yrs	Base: ₹28.5lakhs Stocks: - Bonus: ₹4.4lakhs CTC:₹32.9lakhs	Government College of Technology Kongu Polytechnic College	Area Optimization Voltus Microarchitecture Tcsh Universal Verification Methodology (Uvm) Test Planning (Show More) Assertion Based Verification Field-programmable Gate Arrays (Fpga) Simvision Tempus Cadence Virtuoso Physical Design Innovus Genus Conformal Jasper Gold Python Xcelium Vim Bash Digital Circuit Design Rtl Design Conformal Lec Computer Hardware Troubleshooting Verilog Hdl Perl Git Linux Centos Windows Computer Hardware C Microsoft Word Microsoft Excel Microsoft Powerpoint Systemverilog Upf Tcl Modelsim Circuit Analysis Computer Hardware Assembly Computer Hardware Installation Rtl Coding Logic Synthesis Cdc Lint Static Timing Analysis Low-power Design Application-specific Integrated Circuits (Asic) Computer Architecture System On A Chip (Soc) Finite State Machines Rtl-to-gdsii Flow Formal Verification
Texas Instruments Bengaluru	Digital Design Engineer	3.7yrs	Base: ₹28.5lakhs Stocks: - Bonus: ₹4.4lakhs CTC:₹32.9lakhs	Government College of Technology Kongu Polytechnic College	Area Optimization Voltus Microarchitecture Tcsh Universal Verification Methodology (Uvm) Test Planning (Show More) Assertion Based Verification Field-programmable Gate Arrays (Fpga) Simvision Tempus Cadence Virtuoso Physical Design Innovus Genus Conformal Jasper Gold Python Xcelium Vim Bash Digital Circuit Design Rtl Design Conformal Lec Computer Hardware Troubleshooting Verilog Hdl Perl Git Linux Centos Windows Computer Hardware C Microsoft Word Microsoft Excel Microsoft Powerpoint Systemverilog Upf Tcl Modelsim Circuit Analysis Computer Hardware Assembly Computer Hardware Installation Rtl Coding Logic Synthesis Cdc Lint Static Timing Analysis Low-power Design Application-specific Integrated Circuits (Asic) Computer Architecture System On A Chip (Soc) Finite State Machines Rtl-to-gdsii Flow Formal Verification
Intel Santa Clara	Staff Engineer Male	16.3yrs		Indian Institute of Technology P.g. College of Law	Functional Verification Formal Verification Eda Systemverilog Perl Low Power Design (Show More) Tcl Soc Logic Synthesis Vlsi Asic Rtl Design Power Management Semiconductors Cadence Debugging Verilog Static Timing Analysis Cad Vhdl Physical Design Embedded Systems Open Verification Methodology Integrated Circuit Design Rtl Coding Amba Ahb Usb Analog Arm Timing Closure Modelsim Primetime Fpga Ncsim Ic Cmos Specman Dft
AMD Bangalore	Senior Member Of Technical Staff Male	18.5yrs		Birla Institute of Technology and Science Indian Institute of Technology	Application Specific Integrated Circuits Asic Debugging Digital Signal Processors Eda Embedded Systems (Show More) Ic Integrated Circuits Low Power Design Modelsim Perl Rtl Design Semiconductors Soc System On A Chip Systemverilog Tcl Testing Verilog Very Large Scale Integration Vlsi
Advanced Micro Devices (Amd) Bengaluru	Senior Member Of Technical Staff (L8) Male	18yrs			VLSI Embedded Systems SoC TCL SystemVerilog Perl (Show More) Debugging Verilog ASIC EDA Digital Signal Processors Semiconductors IC ModelSim Testing Integrated Circuits (IC) RTL design Low-power Design System on a Chip (SoC)
AMD Bengaluru	Senior Silicon Design Engineer	5.4yrs	Base: ₹28.5lakhs Stocks: ₹8.6lakhs Bonus: ₹3.1lakhs CTC:₹40.2lakhs		Logic Synthesis Pnr Clocking Timing Closure Timing Primetime (Show More) Verilog Cadence Virtuoso Mentor Graphics C Modelsim Xilinx Cadence Innovus Cadence Genus Field-programmable Gate Arrays (Fpga) Cmos Vlsi System On A Chip (Soc) Tcl-tk Perl Sta Gpu Tcl Synopsys Primetime Low-power Design
Smartsocs	Director	16.6yrs		Birla Institute of Technology and Science Annamalai University	VLSI Embedded Systems SoC TCL SystemVerilog Perl (Show More) Debugging Verilog ASIC EDA Digital Signal Processors Semiconductors IC ModelSim Testing Integrated Circuits (IC) RTL design Low-power Design System on a Chip (SoC)

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Frequently asked questions

How much do Low Power Design employees make?

Employees who know Low Power Design earn an average of ₹47.9lakhs, mostly ranging from ₹34.3lakhs per year to ₹106.1lakhs per year based on 11 profiles. The top 10% of employees earn more than ₹77.7lakhs per year.

What is the average salary of Low Power Design?

Average salary of an employee who know Low Power Design is ₹47.9lakhs.

What is the median salary offered who know Low Power Design?

The median salary approximately calculated from salary profiles measured so far is ₹40.2lakhs per year.

How is the age distributed among employees who know Low Power Design?

27% of employees lie between 21-26 yrs . 27% of the employees fall in the age group of 26-31 yrs .

Frequently asked questions

How much do Low Power Design employees make?

What is the average salary of Low Power Design?

Average salary of an employee who know Low Power Design is ₹47.9lakhs.

What is the median salary offered who know Low Power Design?

The median salary approximately calculated from salary profiles measured so far is ₹40.2lakhs per year.

How is the age distributed among employees who know Low Power Design?

27% of employees lie between 21-26 yrs . 27% of the employees fall in the age group of 26-31 yrs .

Salary Brackets

Percentage
10-20 lakhs	10-20 lakhs Percentage : 9
30-40 lakhs	30-40 lakhs Percentage : 36
40-50 lakhs	40-50 lakhs Percentage : 36
> 50 lakhs	> 50 lakhs Percentage : 18

Age Brackets

Percentage
21-26 yrs	21-26 yrs Percentage : 27
26-31 yrs	26-31 yrs Percentage : 27
36-41 yrs	36-41 yrs Percentage : 18
> 41 yrs	> 41 yrs Percentage : 9

Skills

Trending

low power design

100 %

perl

0 %

tcl

0 %

modelsim

0 %

verilog

0 %

rtl design

0 %

system on a chip (soc)

0 %

Schools

Top

Government College of Technology

27 %

Kongu Polytechnic College

27 %

Birla Institute of Technology and Science

18 %

Indian Institute of Technology

18 %

Annamalai University

9 %

Indian Institute of Technology (Banaras Hindu University)

9 %

Nirma University

9 %

Low Power Design Salaries

Average salary is ₹47.9lakhs.

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How much do Low Power Design employees make?

What is the average salary of Low Power Design?

What is the median salary offered who know Low Power Design?

How is the age distributed among employees who know Low Power Design?

How much do Low Power Design employees make?

What is the average salary of Low Power Design?

What is the median salary offered who know Low Power Design?

How is the age distributed among employees who know Low Power Design?

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